Lines Matching refs:CodeGenRegBank
62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter()
67 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
70 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
74 CodeGenRegBank &Bank);
78 CodeGenRegBank &Bank);
91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
103 CodeGenTarget &Target, CodeGenRegBank &Bank) { in runEnums()
208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure()
697 CodeGenRegBank &RegBank, in emitComposeSubRegIndices()
767 CodeGenRegBank &RegBank, in emitComposeSubRegIndexLaneMask()
874 CodeGenRegBank &RegBank) { in runMCDesc()
1145 CodeGenRegBank &RegBank) { in runTargetHeader()
1221 CodeGenRegBank &RegBank){ in runTargetDesc()
1705 CodeGenRegBank &RegBank = Target.getRegBank(); in run()
1723 CodeGenRegBank &RegBank = Target.getRegBank(); in debugDump()