Lines Matching refs:DISABLED
4 …le-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU-DISABLED
5 …ble-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=NVPTX-DISABLED
2803 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2804 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
2805 ; AMDGPU-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {
2806 ; AMDGPU-DISABLED-NEXT: entry:
2807 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2808 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2809 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0…
2810 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
2811 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
2812 ; AMDGPU-DISABLED: user_code.entry:
2813 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2814 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_A…
2815 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
2816 ; AMDGPU-DISABLED-NEXT: ret void
2817 ; AMDGPU-DISABLED: worker.exit:
2818 ; AMDGPU-DISABLED-NEXT: ret void
2821 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2822 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__
2823 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2824 ; AMDGPU-DISABLED-NEXT: entry:
2825 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2826 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2827 ; AMDGPU-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8:[0-9]+]]
2828 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9:[0-9]+]]
2829 ; AMDGPU-DISABLED-NEXT: ret void
2832 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
2833 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
2834 ; AMDGPU-DISABLED-SAME: () #[[ATTR1:[0-9]+]] {
2835 ; AMDGPU-DISABLED-NEXT: entry:
2836 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2837 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB2]], i32 …
2838 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
2839 ; AMDGPU-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
2840 ; AMDGPU-DISABLED: omp_if.then:
2841 ; AMDGPU-DISABLED-NEXT: store i32 0, i32* @G, align 4
2842 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) …
2843 ; AMDGPU-DISABLED-NEXT: br label [[OMP_IF_END]]
2844 ; AMDGPU-DISABLED: omp_if.end:
2845 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0…
2846 ; AMDGPU-DISABLED-NEXT: ret void
2849 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
2850 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here
2851 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
2852 ; AMDGPU-DISABLED-NEXT: entry:
2853 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2854 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB2]], i32 …
2855 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
2856 ; AMDGPU-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
2857 ; AMDGPU-DISABLED: omp_if.then:
2858 ; AMDGPU-DISABLED-NEXT: store i32 0, i32* @G, align 4
2859 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
2860 ; AMDGPU-DISABLED-NEXT: br label [[OMP_IF_END]]
2861 ; AMDGPU-DISABLED: omp_if.end:
2862 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]])
2863 ; AMDGPU-DISABLED-NEXT: ret void
2866 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2867 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
2868 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
2869 ; AMDGPU-DISABLED-NEXT: entry:
2870 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2871 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2872 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
2873 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
2874 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
2875 ; AMDGPU-DISABLED: user_code.entry:
2876 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2877 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
2878 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
2879 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
2880 ; AMDGPU-DISABLED-NEXT: ret void
2881 ; AMDGPU-DISABLED: worker.exit:
2882 ; AMDGPU-DISABLED-NEXT: ret void
2885 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2886 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__1
2887 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2888 ; AMDGPU-DISABLED-NEXT: entry:
2889 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2890 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2891 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
2892 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
2893 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2894 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
2895 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2896 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2897 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
2898 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
2899 ; AMDGPU-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8]]
2900 ; AMDGPU-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
2901 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
2902 ; AMDGPU-DISABLED-NEXT: ret void
2905 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2906 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2
2907 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2908 ; AMDGPU-DISABLED-NEXT: entry:
2909 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2910 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2911 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10:[0-9]+]]
2912 ; AMDGPU-DISABLED-NEXT: ret void
2915 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2916 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
2917 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
2918 ; AMDGPU-DISABLED-NEXT: entry:
2919 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
2920 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
2921 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2922 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
2923 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
2924 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
2925 ; AMDGPU-DISABLED-NEXT: ret void
2928 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2929 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3
2930 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2931 ; AMDGPU-DISABLED-NEXT: entry:
2932 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2933 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2934 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
2935 ; AMDGPU-DISABLED-NEXT: ret void
2938 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2939 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
2940 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
2941 ; AMDGPU-DISABLED-NEXT: entry:
2942 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
2943 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
2944 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2945 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
2946 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
2947 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
2948 ; AMDGPU-DISABLED-NEXT: ret void
2951 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2952 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interpro…
2953 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
2954 ; AMDGPU-DISABLED-NEXT: entry:
2955 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2956 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2957 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
2958 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
2959 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
2960 ; AMDGPU-DISABLED: user_code.entry:
2961 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2962 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
2963 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
2964 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
2965 ; AMDGPU-DISABLED-NEXT: ret void
2966 ; AMDGPU-DISABLED: worker.exit:
2967 ; AMDGPU-DISABLED-NEXT: ret void
2970 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2971 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__4
2972 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2973 ; AMDGPU-DISABLED-NEXT: entry:
2974 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2975 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2976 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
2977 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2978 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
2979 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[…
2980 ; AMDGPU-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8]]
2981 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2982 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2983 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
2984 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
2985 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[…
2986 ; AMDGPU-DISABLED-NEXT: ret void
2989 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
2990 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
2991 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
2992 ; AMDGPU-DISABLED-NEXT: entry:
2993 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
2994 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2995 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
2996 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
2997 ; AMDGPU-DISABLED-NEXT: ret void
3000 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3001 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
3002 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3003 ; AMDGPU-DISABLED-NEXT: entry:
3004 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3005 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3006 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3007 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3008 ; AMDGPU-DISABLED-NEXT: ret void
3011 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3012 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5
3013 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3014 ; AMDGPU-DISABLED-NEXT: entry:
3015 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3016 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3017 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3018 ; AMDGPU-DISABLED-NEXT: ret void
3021 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3022 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
3023 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3024 ; AMDGPU-DISABLED-NEXT: entry:
3025 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3026 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3027 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3028 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3029 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3030 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
3031 ; AMDGPU-DISABLED-NEXT: ret void
3034 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3035 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
3036 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3037 ; AMDGPU-DISABLED-NEXT: entry:
3038 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3039 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3040 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3041 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3042 ; AMDGPU-DISABLED-NEXT: ret void
3045 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3046 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
3047 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3048 ; AMDGPU-DISABLED-NEXT: entry:
3049 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3050 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3051 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3052 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3053 ; AMDGPU-DISABLED-NEXT: ret void
3056 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3057 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fal…
3058 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3059 ; AMDGPU-DISABLED-NEXT: entry:
3060 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3061 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3062 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3063 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3064 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3065 ; AMDGPU-DISABLED: user_code.entry:
3066 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3067 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3068 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
3069 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3070 ; AMDGPU-DISABLED-NEXT: ret void
3071 ; AMDGPU-DISABLED: worker.exit:
3072 ; AMDGPU-DISABLED-NEXT: ret void
3075 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3076 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__6
3077 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3078 ; AMDGPU-DISABLED-NEXT: entry:
3079 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3080 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3081 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3082 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3083 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3084 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3085 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3086 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3087 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3088 ; AMDGPU-DISABLED-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR10]]
3089 ; AMDGPU-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3090 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3091 ; AMDGPU-DISABLED-NEXT: ret void
3094 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3095 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7
3096 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3097 ; AMDGPU-DISABLED-NEXT: entry:
3098 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3099 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3100 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3101 ; AMDGPU-DISABLED-NEXT: ret void
3104 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3105 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
3106 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3107 ; AMDGPU-DISABLED-NEXT: entry:
3108 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3109 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3110 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3111 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3112 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3113 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
3114 ; AMDGPU-DISABLED-NEXT: ret void
3117 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3118 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8
3119 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3120 ; AMDGPU-DISABLED-NEXT: entry:
3121 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3122 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3123 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3124 ; AMDGPU-DISABLED-NEXT: ret void
3127 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3128 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
3129 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3130 ; AMDGPU-DISABLED-NEXT: entry:
3131 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3132 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3133 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3134 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3135 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3136 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
3137 ; AMDGPU-DISABLED-NEXT: ret void
3140 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3141 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openm…
3142 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3143 ; AMDGPU-DISABLED-NEXT: entry:
3144 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3145 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3146 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3147 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3148 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3149 ; AMDGPU-DISABLED: user_code.entry:
3150 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3151 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3152 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
3153 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3154 ; AMDGPU-DISABLED-NEXT: ret void
3155 ; AMDGPU-DISABLED: worker.exit:
3156 ; AMDGPU-DISABLED-NEXT: ret void
3159 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3160 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__9
3161 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3162 ; AMDGPU-DISABLED-NEXT: entry:
3163 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3164 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3165 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3166 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3167 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3168 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3169 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3170 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3171 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3172 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
3173 ; AMDGPU-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3174 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3175 ; AMDGPU-DISABLED-NEXT: ret void
3178 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3179 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10
3180 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3181 ; AMDGPU-DISABLED-NEXT: entry:
3182 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3183 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3184 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3185 ; AMDGPU-DISABLED-NEXT: ret void
3188 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3189 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
3190 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3191 ; AMDGPU-DISABLED-NEXT: entry:
3192 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3193 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3194 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3195 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3196 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3197 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3198 ; AMDGPU-DISABLED-NEXT: ret void
3201 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3202 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11
3203 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3204 ; AMDGPU-DISABLED-NEXT: entry:
3205 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3206 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3207 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3208 ; AMDGPU-DISABLED-NEXT: ret void
3211 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3212 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
3213 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3214 ; AMDGPU-DISABLED-NEXT: entry:
3215 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3216 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3217 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3218 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3219 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3220 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3221 ; AMDGPU-DISABLED-NEXT: ret void
3224 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3225 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
3226 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3227 ; AMDGPU-DISABLED-NEXT: entry:
3228 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3229 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3230 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3231 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3232 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3233 ; AMDGPU-DISABLED: user_code.entry:
3234 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3235 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3236 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__12(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO…
3237 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3238 ; AMDGPU-DISABLED-NEXT: ret void
3239 ; AMDGPU-DISABLED: worker.exit:
3240 ; AMDGPU-DISABLED-NEXT: ret void
3243 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3244 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__12
3245 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3246 ; AMDGPU-DISABLED-NEXT: entry:
3247 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3248 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3249 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3250 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3251 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3252 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
3253 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3254 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3255 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3256 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3257 ; AMDGPU-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3258 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3259 ; AMDGPU-DISABLED-NEXT: ret void
3262 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3263 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13
3264 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3265 ; AMDGPU-DISABLED-NEXT: entry:
3266 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3267 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3268 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3269 ; AMDGPU-DISABLED-NEXT: ret void
3272 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3273 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
3274 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3275 ; AMDGPU-DISABLED-NEXT: entry:
3276 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3277 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3278 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3279 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3280 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3281 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3282 ; AMDGPU-DISABLED-NEXT: ret void
3285 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3286 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14
3287 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3288 ; AMDGPU-DISABLED-NEXT: entry:
3289 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3290 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3291 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3292 ; AMDGPU-DISABLED-NEXT: ret void
3295 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3296 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
3297 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3298 ; AMDGPU-DISABLED-NEXT: entry:
3299 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3300 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3301 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3302 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3303 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3304 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3305 ; AMDGPU-DISABLED-NEXT: ret void
3308 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3309 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interpro…
3310 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3311 ; AMDGPU-DISABLED-NEXT: entry:
3312 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3313 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3314 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3315 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3316 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3317 ; AMDGPU-DISABLED: user_code.entry:
3318 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3319 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__15(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO…
3320 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3321 ; AMDGPU-DISABLED-NEXT: ret void
3322 ; AMDGPU-DISABLED: worker.exit:
3323 ; AMDGPU-DISABLED-NEXT: ret void
3326 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3327 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__15
3328 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3329 ; AMDGPU-DISABLED-NEXT: entry:
3330 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3331 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3332 ; AMDGPU-DISABLED-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @omp_get_thread_num to i32 (…
3333 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.i…
3334 ; AMDGPU-DISABLED-NEXT: ret void
3337 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3338 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_aft…
3339 ; AMDGPU-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
3340 ; AMDGPU-DISABLED-NEXT: entry:
3341 ; AMDGPU-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3342 ; AMDGPU-DISABLED-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3343 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3344 ; AMDGPU-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
3345 ; AMDGPU-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
3346 ; AMDGPU-DISABLED: if.then:
3347 ; AMDGPU-DISABLED-NEXT: br label [[RETURN:%.*]]
3348 ; AMDGPU-DISABLED: if.end:
3349 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3350 ; AMDGPU-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
3351 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.i…
3352 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_a…
3353 ; AMDGPU-DISABLED-NEXT: br label [[RETURN]]
3354 ; AMDGPU-DISABLED: return:
3355 ; AMDGPU-DISABLED-NEXT: ret void
3358 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3359 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_aft…
3360 ; AMDGPU-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
3361 ; AMDGPU-DISABLED-NEXT: entry:
3362 ; AMDGPU-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3363 ; AMDGPU-DISABLED-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3364 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3365 ; AMDGPU-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
3366 ; AMDGPU-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
3367 ; AMDGPU-DISABLED: if.then:
3368 ; AMDGPU-DISABLED-NEXT: br label [[RETURN:%.*]]
3369 ; AMDGPU-DISABLED: if.end:
3370 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3371 ; AMDGPU-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
3372 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after(i…
3373 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_a…
3374 ; AMDGPU-DISABLED-NEXT: br label [[RETURN]]
3375 ; AMDGPU-DISABLED: return:
3376 ; AMDGPU-DISABLED-NEXT: ret void
3379 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3380 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_…
3381 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3382 ; AMDGPU-DISABLED-NEXT: entry:
3383 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3384 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3385 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3386 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3387 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3388 ; AMDGPU-DISABLED: user_code.entry:
3389 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3390 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__16(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO…
3391 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3392 ; AMDGPU-DISABLED-NEXT: ret void
3393 ; AMDGPU-DISABLED: worker.exit:
3394 ; AMDGPU-DISABLED-NEXT: ret void
3397 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3398 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__16
3399 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3400 ; AMDGPU-DISABLED-NEXT: entry:
3401 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3402 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3403 ; AMDGPU-DISABLED-NEXT: call void @weak_callee_empty() #[[ATTR8]]
3404 ; AMDGPU-DISABLED-NEXT: ret void
3407 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3408 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@weak_callee_empty
3409 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3410 ; AMDGPU-DISABLED-NEXT: entry:
3411 ; AMDGPU-DISABLED-NEXT: ret void
3414 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3415 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17
3416 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3417 ; AMDGPU-DISABLED-NEXT: entry:
3418 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3419 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3420 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3421 ; AMDGPU-DISABLED-NEXT: ret void
3424 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3425 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
3426 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3427 ; AMDGPU-DISABLED-NEXT: entry:
3428 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3429 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3430 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3431 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3432 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3433 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3434 ; AMDGPU-DISABLED-NEXT: ret void
3437 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3438 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18
3439 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3440 ; AMDGPU-DISABLED-NEXT: entry:
3441 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3442 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3443 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3444 ; AMDGPU-DISABLED-NEXT: ret void
3447 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3448 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
3449 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3450 ; AMDGPU-DISABLED-NEXT: entry:
3451 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3452 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3453 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3454 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3455 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3456 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3457 ; AMDGPU-DISABLED-NEXT: ret void
3460 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3461 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_aft…
3462 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3463 ; AMDGPU-DISABLED-NEXT: entry:
3464 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3465 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3466 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3467 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3468 ; AMDGPU-DISABLED-NEXT: ret void
3471 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3472 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_aft…
3473 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3474 ; AMDGPU-DISABLED-NEXT: entry:
3475 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3476 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3477 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3478 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3479 ; AMDGPU-DISABLED-NEXT: ret void
3482 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3483 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19
3484 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3485 ; AMDGPU-DISABLED-NEXT: entry:
3486 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3487 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3488 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3489 ; AMDGPU-DISABLED-NEXT: ret void
3492 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3493 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
3494 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3495 ; AMDGPU-DISABLED-NEXT: entry:
3496 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3497 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3498 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3499 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3500 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3501 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3502 ; AMDGPU-DISABLED-NEXT: ret void
3505 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3506 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
3507 ; NVPTX-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {
3508 ; NVPTX-DISABLED-NEXT: entry:
3509 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3510 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3511 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-…
3512 ; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3513 ; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_E…
3514 ; NVPTX-DISABLED: user_code.entry:
3515 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3516 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_AD…
3517 ; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tru…
3518 ; NVPTX-DISABLED-NEXT: ret void
3519 ; NVPTX-DISABLED: worker.exit:
3520 ; NVPTX-DISABLED-NEXT: ret void
3523 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3524 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__
3525 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3526 ; NVPTX-DISABLED-NEXT: entry:
3527 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3528 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3529 ; NVPTX-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8:[0-9]+]]
3530 ; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9:[0-9]+]]
3531 ; NVPTX-DISABLED-NEXT: ret void
3534 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
3535 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
3536 ; NVPTX-DISABLED-SAME: () #[[ATTR1:[0-9]+]] {
3537 ; NVPTX-DISABLED-NEXT: entry:
3538 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3539 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB2]], i32 […
3540 ; NVPTX-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
3541 ; NVPTX-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
3542 ; NVPTX-DISABLED: omp_if.then:
3543 ; NVPTX-DISABLED-NEXT: store i32 0, i32* @G, align 4
3544 ; NVPTX-DISABLED-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) #…
3545 ; NVPTX-DISABLED-NEXT: br label [[OMP_IF_END]]
3546 ; NVPTX-DISABLED: omp_if.end:
3547 ; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]…
3548 ; NVPTX-DISABLED-NEXT: ret void
3551 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
3552 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here
3553 ; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
3554 ; NVPTX-DISABLED-NEXT: entry:
3555 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3556 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB2]], i32 […
3557 ; NVPTX-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
3558 ; NVPTX-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
3559 ; NVPTX-DISABLED: omp_if.then:
3560 ; NVPTX-DISABLED-NEXT: store i32 0, i32* @G, align 4
3561 ; NVPTX-DISABLED-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
3562 ; NVPTX-DISABLED-NEXT: br label [[OMP_IF_END]]
3563 ; NVPTX-DISABLED: omp_if.end:
3564 ; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]])
3565 ; NVPTX-DISABLED-NEXT: ret void
3568 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3569 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
3570 ; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
3571 ; NVPTX-DISABLED-NEXT: entry:
3572 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3573 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3574 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], …
3575 ; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3576 ; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_E…
3577 ; NVPTX-DISABLED: user_code.entry:
3578 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3579 ; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3580 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_A…
3581 ; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tru…
3582 ; NVPTX-DISABLED-NEXT: ret void
3583 ; NVPTX-DISABLED: worker.exit:
3584 ; NVPTX-DISABLED-NEXT: ret void
3587 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3588 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__1
3589 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3590 ; NVPTX-DISABLED-NEXT: entry:
3591 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3592 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3593 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3594 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3595 ; NVPTX-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3596 ; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
3597 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3598 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3599 ; NVPTX-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3600 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], …
3601 ; NVPTX-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8]]
3602 ; NVPTX-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3603 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], …
3604 ; NVPTX-DISABLED-NEXT: ret void
3607 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3608 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2
3609 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3610 ; NVPTX-DISABLED-NEXT: entry:
3611 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3612 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3613 ; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR10:[0-9]+]]
3614 ; NVPTX-DISABLED-NEXT: ret void
3617 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3618 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
3619 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3620 ; NVPTX-DISABLED-NEXT: entry:
3621 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3622 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3623 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3624 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3625 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3626 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[…
3627 ; NVPTX-DISABLED-NEXT: ret void
3630 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3631 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3
3632 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3633 ; NVPTX-DISABLED-NEXT: entry:
3634 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3635 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3636 ; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3637 ; NVPTX-DISABLED-NEXT: ret void
3640 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3641 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
3642 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3643 ; NVPTX-DISABLED-NEXT: entry:
3644 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3645 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3646 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3647 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3648 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3649 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[…
3650 ; NVPTX-DISABLED-NEXT: ret void
3653 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3654 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interproc…
3655 ; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
3656 ; NVPTX-DISABLED-NEXT: entry:
3657 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3658 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3659 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], …
3660 ; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3661 ; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_E…
3662 ; NVPTX-DISABLED: user_code.entry:
3663 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3664 ; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3665 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_A…
3666 ; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tru…
3667 ; NVPTX-DISABLED-NEXT: ret void
3668 ; NVPTX-DISABLED: worker.exit:
3669 ; NVPTX-DISABLED-NEXT: ret void
3672 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3673 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__4
3674 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3675 ; NVPTX-DISABLED-NEXT: entry:
3676 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3677 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3678 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3679 ; NVPTX-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3680 ; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
3681 ; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[[…
3682 ; NVPTX-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8]]
3683 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3684 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3685 ; NVPTX-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3686 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], …
3687 ; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[A…
3688 ; NVPTX-DISABLED-NEXT: ret void
3691 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
3692 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
3693 ; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
3694 ; NVPTX-DISABLED-NEXT: entry:
3695 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3696 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3697 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3698 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], …
3699 ; NVPTX-DISABLED-NEXT: ret void
3702 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
3703 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
3704 ; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
3705 ; NVPTX-DISABLED-NEXT: entry:
3706 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3707 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3708 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3709 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], …
3710 ; NVPTX-DISABLED-NEXT: ret void
3713 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3714 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5
3715 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3716 ; NVPTX-DISABLED-NEXT: entry:
3717 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3718 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3719 ; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3720 ; NVPTX-DISABLED-NEXT: ret void
3723 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3724 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
3725 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3726 ; NVPTX-DISABLED-NEXT: entry:
3727 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3728 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3729 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3730 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3731 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3732 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[…
3733 ; NVPTX-DISABLED-NEXT: ret void
3736 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
3737 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
3738 ; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
3739 ; NVPTX-DISABLED-NEXT: entry:
3740 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3741 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3742 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3743 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], …
3744 ; NVPTX-DISABLED-NEXT: ret void
3747 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
3748 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
3749 ; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
3750 ; NVPTX-DISABLED-NEXT: entry:
3751 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3752 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3753 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3754 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], …
3755 ; NVPTX-DISABLED-NEXT: ret void
3758 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3759 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fall…
3760 ; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
3761 ; NVPTX-DISABLED-NEXT: entry:
3762 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3763 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3764 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], …
3765 ; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3766 ; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_E…
3767 ; NVPTX-DISABLED: user_code.entry:
3768 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3769 ; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3770 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_A…
3771 ; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tru…
3772 ; NVPTX-DISABLED-NEXT: ret void
3773 ; NVPTX-DISABLED: worker.exit:
3774 ; NVPTX-DISABLED-NEXT: ret void
3777 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3778 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__6
3779 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3780 ; NVPTX-DISABLED-NEXT: entry:
3781 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3782 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3783 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3784 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3785 ; NVPTX-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3786 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3787 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3788 ; NVPTX-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3789 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], …
3790 ; NVPTX-DISABLED-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR10]]
3791 ; NVPTX-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3792 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], …
3793 ; NVPTX-DISABLED-NEXT: ret void
3796 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3797 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7
3798 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3799 ; NVPTX-DISABLED-NEXT: entry:
3800 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3801 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3802 ; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3803 ; NVPTX-DISABLED-NEXT: ret void
3806 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3807 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
3808 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3809 ; NVPTX-DISABLED-NEXT: entry:
3810 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3811 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3812 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3813 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3814 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3815 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[…
3816 ; NVPTX-DISABLED-NEXT: ret void
3819 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3820 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8
3821 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3822 ; NVPTX-DISABLED-NEXT: entry:
3823 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3824 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3825 ; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3826 ; NVPTX-DISABLED-NEXT: ret void
3829 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3830 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
3831 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3832 ; NVPTX-DISABLED-NEXT: entry:
3833 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3834 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3835 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3836 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3837 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3838 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[…
3839 ; NVPTX-DISABLED-NEXT: ret void
3842 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3843 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp…
3844 ; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
3845 ; NVPTX-DISABLED-NEXT: entry:
3846 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3847 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3848 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], …
3849 ; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3850 ; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_E…
3851 ; NVPTX-DISABLED: user_code.entry:
3852 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3853 ; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3854 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_A…
3855 ; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tru…
3856 ; NVPTX-DISABLED-NEXT: ret void
3857 ; NVPTX-DISABLED: worker.exit:
3858 ; NVPTX-DISABLED-NEXT: ret void
3861 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3862 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__9
3863 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3864 ; NVPTX-DISABLED-NEXT: entry:
3865 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3866 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3867 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3868 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3869 ; NVPTX-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3870 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3871 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3872 ; NVPTX-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3873 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], …
3874 ; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
3875 ; NVPTX-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3876 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], …
3877 ; NVPTX-DISABLED-NEXT: ret void
3880 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3881 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10
3882 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3883 ; NVPTX-DISABLED-NEXT: entry:
3884 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3885 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3886 ; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3887 ; NVPTX-DISABLED-NEXT: ret void
3890 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3891 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
3892 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3893 ; NVPTX-DISABLED-NEXT: entry:
3894 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3895 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3896 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3897 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3898 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3899 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
3900 ; NVPTX-DISABLED-NEXT: ret void
3903 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3904 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11
3905 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3906 ; NVPTX-DISABLED-NEXT: entry:
3907 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3908 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3909 ; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3910 ; NVPTX-DISABLED-NEXT: ret void
3913 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3914 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
3915 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3916 ; NVPTX-DISABLED-NEXT: entry:
3917 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3918 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3919 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3920 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3921 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3922 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
3923 ; NVPTX-DISABLED-NEXT: ret void
3926 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3927 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
3928 ; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
3929 ; NVPTX-DISABLED-NEXT: entry:
3930 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3931 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3932 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], …
3933 ; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3934 ; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_E…
3935 ; NVPTX-DISABLED: user_code.entry:
3936 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
3937 ; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3938 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__12(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
3939 ; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tru…
3940 ; NVPTX-DISABLED-NEXT: ret void
3941 ; NVPTX-DISABLED: worker.exit:
3942 ; NVPTX-DISABLED-NEXT: ret void
3945 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3946 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__12
3947 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3948 ; NVPTX-DISABLED-NEXT: entry:
3949 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3950 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3951 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3952 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3953 ; NVPTX-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3954 ; NVPTX-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
3955 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3956 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3957 ; NVPTX-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3958 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], …
3959 ; NVPTX-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3960 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], …
3961 ; NVPTX-DISABLED-NEXT: ret void
3964 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3965 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13
3966 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3967 ; NVPTX-DISABLED-NEXT: entry:
3968 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3969 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3970 ; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3971 ; NVPTX-DISABLED-NEXT: ret void
3974 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3975 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
3976 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3977 ; NVPTX-DISABLED-NEXT: entry:
3978 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3979 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3980 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3981 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3982 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3983 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
3984 ; NVPTX-DISABLED-NEXT: ret void
3987 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3988 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14
3989 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
3990 ; NVPTX-DISABLED-NEXT: entry:
3991 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3992 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3993 ; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3994 ; NVPTX-DISABLED-NEXT: ret void
3997 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3998 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
3999 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
4000 ; NVPTX-DISABLED-NEXT: entry:
4001 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
4002 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
4003 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
4004 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
4005 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
4006 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
4007 ; NVPTX-DISABLED-NEXT: ret void
4010 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4011 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interproc…
4012 ; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
4013 ; NVPTX-DISABLED-NEXT: entry:
4014 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
4015 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4016 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], …
4017 ; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
4018 ; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_E…
4019 ; NVPTX-DISABLED: user_code.entry:
4020 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
4021 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__15(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
4022 ; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tru…
4023 ; NVPTX-DISABLED-NEXT: ret void
4024 ; NVPTX-DISABLED: worker.exit:
4025 ; NVPTX-DISABLED-NEXT: ret void
4028 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4029 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__15
4030 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
4031 ; NVPTX-DISABLED-NEXT: entry:
4032 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4033 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4034 ; NVPTX-DISABLED-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @omp_get_thread_num to i32 ()…
4035 ; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.in…
4036 ; NVPTX-DISABLED-NEXT: ret void
4039 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
4040 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_afte…
4041 ; NVPTX-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
4042 ; NVPTX-DISABLED-NEXT: entry:
4043 ; NVPTX-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4044 ; NVPTX-DISABLED-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4045 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4046 ; NVPTX-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
4047 ; NVPTX-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
4048 ; NVPTX-DISABLED: if.then:
4049 ; NVPTX-DISABLED-NEXT: br label [[RETURN:%.*]]
4050 ; NVPTX-DISABLED: if.end:
4051 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4052 ; NVPTX-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
4053 ; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.in…
4054 ; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_af…
4055 ; NVPTX-DISABLED-NEXT: br label [[RETURN]]
4056 ; NVPTX-DISABLED: return:
4057 ; NVPTX-DISABLED-NEXT: ret void
4060 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
4061 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
4062 ; NVPTX-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
4063 ; NVPTX-DISABLED-NEXT: entry:
4064 ; NVPTX-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4065 ; NVPTX-DISABLED-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4066 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4067 ; NVPTX-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
4068 ; NVPTX-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
4069 ; NVPTX-DISABLED: if.then:
4070 ; NVPTX-DISABLED-NEXT: br label [[RETURN:%.*]]
4071 ; NVPTX-DISABLED: if.end:
4072 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4073 ; NVPTX-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
4074 ; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after(i3…
4075 ; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_af…
4076 ; NVPTX-DISABLED-NEXT: br label [[RETURN]]
4077 ; NVPTX-DISABLED: return:
4078 ; NVPTX-DISABLED-NEXT: ret void
4081 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4082 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l…
4083 ; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
4084 ; NVPTX-DISABLED-NEXT: entry:
4085 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
4086 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4087 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], …
4088 ; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
4089 ; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_E…
4090 ; NVPTX-DISABLED: user_code.entry:
4091 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
4092 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__16(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
4093 ; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tru…
4094 ; NVPTX-DISABLED-NEXT: ret void
4095 ; NVPTX-DISABLED: worker.exit:
4096 ; NVPTX-DISABLED-NEXT: ret void
4099 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4100 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__16
4101 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
4102 ; NVPTX-DISABLED-NEXT: entry:
4103 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4104 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4105 ; NVPTX-DISABLED-NEXT: call void @weak_callee_empty() #[[ATTR8]]
4106 ; NVPTX-DISABLED-NEXT: ret void
4109 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
4110 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@weak_callee_empty
4111 ; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
4112 ; NVPTX-DISABLED-NEXT: entry:
4113 ; NVPTX-DISABLED-NEXT: ret void
4116 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4117 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17
4118 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
4119 ; NVPTX-DISABLED-NEXT: entry:
4120 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4121 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4122 ; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR10]]
4123 ; NVPTX-DISABLED-NEXT: ret void
4126 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4127 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
4128 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
4129 ; NVPTX-DISABLED-NEXT: entry:
4130 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
4131 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
4132 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
4133 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
4134 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
4135 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
4136 ; NVPTX-DISABLED-NEXT: ret void
4139 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4140 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18
4141 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
4142 ; NVPTX-DISABLED-NEXT: entry:
4143 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4144 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4145 ; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR10]]
4146 ; NVPTX-DISABLED-NEXT: ret void
4149 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4150 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
4151 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
4152 ; NVPTX-DISABLED-NEXT: entry:
4153 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
4154 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
4155 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
4156 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
4157 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
4158 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
4159 ; NVPTX-DISABLED-NEXT: ret void
4162 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
4163 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_afte…
4164 ; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
4165 ; NVPTX-DISABLED-NEXT: entry:
4166 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
4167 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
4168 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
4169 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], …
4170 ; NVPTX-DISABLED-NEXT: ret void
4173 ; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
4174 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_afte…
4175 ; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
4176 ; NVPTX-DISABLED-NEXT: entry:
4177 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
4178 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLO…
4179 ; NVPTX-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
4180 ; NVPTX-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], …
4181 ; NVPTX-DISABLED-NEXT: ret void
4184 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4185 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19
4186 ; NVPTX-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[…
4187 ; NVPTX-DISABLED-NEXT: entry:
4188 ; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4189 ; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4190 ; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR10]]
4191 ; NVPTX-DISABLED-NEXT: ret void
4194 ; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
4195 ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
4196 ; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
4197 ; NVPTX-DISABLED-NEXT: entry:
4198 ; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
4199 ; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
4200 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
4201 ; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
4202 ; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
4203 ; NVPTX-DISABLED-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
4204 ; NVPTX-DISABLED-NEXT: ret void