Lines Matching refs:INDEX
20 ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_C…
26 ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 0
34 ; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[INDEX]], 1
42 ; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[INDEX]], 2
50 ; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[INDEX]], 3
55 ; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
80 ; VF2UF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_…
88 ; VF2UF2-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 0
96 ; VF2UF2-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 1
104 ; VF2UF2-NEXT: [[TMP9:%.*]] = add i32 [[INDEX]], 2
112 ; VF2UF2-NEXT: [[TMP12:%.*]] = add i32 [[INDEX]], 3
117 ; VF2UF2-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
142 ; VF1UF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_…
143 ; VF1UF4-NEXT: [[VEC_IV:%.*]] = add i32 [[INDEX]], 0
144 ; VF1UF4-NEXT: [[VEC_IV4:%.*]] = add i32 [[INDEX]], 1
145 ; VF1UF4-NEXT: [[VEC_IV5:%.*]] = add i32 [[INDEX]], 2
146 ; VF1UF4-NEXT: [[VEC_IV6:%.*]] = add i32 [[INDEX]], 3
153 ; VF1UF4-NEXT: [[INDUCTION:%.*]] = add i32 [[INDEX]], 0
160 ; VF1UF4-NEXT: [[INDUCTION1:%.*]] = add i32 [[INDEX]], 1
167 ; VF1UF4-NEXT: [[INDUCTION2:%.*]] = add i32 [[INDEX]], 2
174 ; VF1UF4-NEXT: [[INDUCTION3:%.*]] = add i32 [[INDEX]], 3
179 ; VF1UF4-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
219 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_C…
225 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0
235 ; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 1
245 ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 2
255 ; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[INDEX]], 3
262 ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
288 ; VF2UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_…
296 ; VF2UF2-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 0
306 ; VF2UF2-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1
316 ; VF2UF2-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 2
326 ; VF2UF2-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], 3
333 ; VF2UF2-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
359 ; VF1UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_…
360 ; VF1UF4-NEXT: [[VEC_IV:%.*]] = add i64 [[INDEX]], 0
361 ; VF1UF4-NEXT: [[VEC_IV4:%.*]] = add i64 [[INDEX]], 1
362 ; VF1UF4-NEXT: [[VEC_IV5:%.*]] = add i64 [[INDEX]], 2
363 ; VF1UF4-NEXT: [[VEC_IV6:%.*]] = add i64 [[INDEX]], 3
370 ; VF1UF4-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0
379 ; VF1UF4-NEXT: [[INDUCTION1:%.*]] = add i64 [[INDEX]], 1
388 ; VF1UF4-NEXT: [[INDUCTION2:%.*]] = add i64 [[INDEX]], 2
397 ; VF1UF4-NEXT: [[INDUCTION3:%.*]] = add i64 [[INDEX]], 3
404 ; VF1UF4-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4