Lines Matching refs:CMP
13 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 0
14 ; CHECK-NEXT: ret i1 [[CMP]]
25 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[SHL_MASK]], 0
26 ; CHECK-NEXT: ret i1 [[CMP]]
37 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[SHL_MASK]], 0
38 ; CHECK-NEXT: ret i1 [[CMP]]
49 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP1]], 0
50 ; CHECK-NEXT: ret i1 [[CMP]]
60 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
61 ; CHECK-NEXT: ret i1 [[CMP]]
71 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[TMP1]], 0
72 ; CHECK-NEXT: ret i1 [[CMP]]
83 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0
84 ; CHECK-NEXT: ret i1 [[CMP]]
95 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 0
96 ; CHECK-NEXT: ret i1 [[CMP]]
107 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0
108 ; CHECK-NEXT: ret i1 [[CMP]]
120 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP1]], zeroinitializer
121 ; CHECK-NEXT: ret <4 x i1> [[CMP]]
131 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 131072, i32 131072, i32 131072, i32…
132 ; CHECK-NEXT: ret <4 x i1> [[CMP]]
142 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 131072, i32 131072, i32 131072, i32…
143 ; CHECK-NEXT: ret <4 x i1> [[CMP]]
153 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 undef, i32 131072, i32 131072, i32 …
154 ; CHECK-NEXT: ret <4 x i1> [[CMP]]
165 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer
166 ; CHECK-NEXT: ret <4 x i1> [[CMP]]
177 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP1]], zeroinitializer
178 ; CHECK-NEXT: ret <4 x i1> [[CMP]]
189 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer
190 ; CHECK-NEXT: ret <4 x i1> [[CMP]]
204 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[SHL]], 64
205 ; CHECK-NEXT: ret i1 [[CMP]]
219 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[SHL]], 64
220 ; CHECK-NEXT: ret i1 [[CMP]]
230 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[SHL]], 66
231 ; CHECK-NEXT: ret i1 [[CMP]]