Lines Matching refs:DIV

34 ; CHECK-NEXT:    [[DIV:%.*]] = sub <2 x i64> zeroinitializer, [[X:%.*]]
35 ; CHECK-NEXT:    ret <2 x i64> [[DIV]]
51 ; CHECK-NEXT:    [[DIV:%.*]] = sub i32 0, [[Y:%.*]]
52 ; CHECK-NEXT:    ret i32 [[DIV]]
61 ; CHECK-NEXT:    [[DIV:%.*]] = sub <2 x i32> zeroinitializer, [[Y:%.*]]
62 ; CHECK-NEXT:    ret <2 x i32> [[DIV]]
92 ; CHECK-NEXT:    [[DIV:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i64>
93 ; CHECK-NEXT:    ret <2 x i64> [[DIV]]
102 ; CHECK-NEXT:    [[DIV:%.*]] = zext i1 [[TMP1]] to i32
103 ; CHECK-NEXT:    ret i32 [[DIV]]
113 ; CHECK-NEXT:    [[DIV:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
114 ; CHECK-NEXT:    ret <2 x i32> [[DIV]]
269 ; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i64> [[X:%.*]], <i64 192, i64 192>
270 ; CHECK-NEXT:    ret <2 x i64> [[DIV]]
323 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[A:%.*]], 3
324 ; CHECK-NEXT:    ret i32 [[DIV]]
333 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[A:%.*]], 4
334 ; CHECK-NEXT:    ret i32 [[DIV]]
343 ; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[A:%.*]], 3
344 ; CHECK-NEXT:    ret i32 [[DIV]]
363 ; CHECK-NEXT:    [[DIV:%.*]] = shl nsw i32 [[A:%.*]], 1
364 ; CHECK-NEXT:    ret i32 [[DIV]]
373 ; CHECK-NEXT:    [[DIV:%.*]] = shl nsw i32 [[A:%.*]], 2
374 ; CHECK-NEXT:    ret i32 [[DIV]]
383 ; CHECK-NEXT:    [[DIV:%.*]] = shl nuw i32 [[A:%.*]], 1
384 ; CHECK-NEXT:    ret i32 [[DIV]]
393 ; CHECK-NEXT:    [[DIV:%.*]] = mul nuw i32 [[A:%.*]], 12
394 ; CHECK-NEXT:    ret i32 [[DIV]]
404 ; CHECK-NEXT:    [[DIV:%.*]] = zext i1 [[TMP1]] to i32
405 ; CHECK-NEXT:    ret i32 [[DIV]]
433 ; CHECK-NEXT:    [[DIV:%.*]] = lshr i32 [[SHL]], 2
434 ; CHECK-NEXT:    [[DIV2:%.*]] = udiv i32 [[A:%.*]], [[DIV]]
445 ; CHECK-NEXT:    [[DIV:%.*]] = udiv exact <2 x i64> [[X:%.*]], <i64 192, i64 192>
446 ; CHECK-NEXT:    ret <2 x i64> [[DIV]]
551 ; CHECK-NEXT:    [[DIV:%.*]] = sub nsw <2 x i8> zeroinitializer, [[DIV1]]
552 ; CHECK-NEXT:    ret <2 x i8> [[DIV]]
635 ; CHECK-NEXT:    [[DIV:%.*]] = sext i8 [[TMP1]] to i32
636 ; CHECK-NEXT:    ret i32 [[DIV]]
648 ; CHECK-NEXT:    [[DIV:%.*]] = zext i1 [[TMP1]] to i32
649 ; CHECK-NEXT:    ret i32 [[DIV]]
661 ; CHECK-NEXT:    [[DIV:%.*]] = sext <3 x i8> [[TMP1]] to <3 x i32>
662 ; CHECK-NEXT:    ret <3 x i32> [[DIV]]
672 ; CHECK-NEXT:    [[DIV:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
673 ; CHECK-NEXT:    ret <2 x i32> [[DIV]]
685 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[CONV]], 128
686 ; CHECK-NEXT:    ret i32 [[DIV]]
926 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv <2 x i8> [[X:%.*]], <i8 -1, i8 1>
927 ; CHECK-NEXT:    [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[DIV]]
939 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv <2 x i8> [[X:%.*]], <i8 -1, i8 -128>
940 ; CHECK-NEXT:    [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[DIV]]
952 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv <2 x i8> [[X:%.*]], <i8 1, i8 -128>
953 ; CHECK-NEXT:    [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[DIV]]
993 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv exact i32 [[X:%.*]], [[Y:%.*]]
994 ; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i32 0, [[DIV]]