Lines Matching refs:ARGC

6 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3
22 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3
38 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3
54 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 3
75 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
91 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
107 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
123 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
140 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
156 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
158 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
176 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
192 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
208 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
224 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
241 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
257 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
259 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
277 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
293 ; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[ARGC:%.*]], <i32 55, i32 55>
309 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
325 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
341 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
358 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
374 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
376 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
394 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
410 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
426 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
442 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
459 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
475 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
477 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
495 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
512 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], 7
532 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
533 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[ARGC]]
548 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
549 ; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[AND]], [[ARGC]]
550 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
551 ; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[AND2]], [[ARGC]]
568 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
585 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], 7
605 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
606 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], [[ARGC]]
621 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
622 ; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[AND]], [[ARGC]]
623 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
624 ; CHECK-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[AND2]], [[ARGC]]
642 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
658 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
674 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
690 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
708 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
724 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
740 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
756 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 23
775 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
791 ; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]]
793 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC]]
812 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
828 ; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
830 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC]], [[ARGC3:%.*]]
849 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
865 ; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]]
867 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[ARGC3:%.*]], [[ARGC]]
888 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
908 ; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]]
910 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[DE]], [[ARGC]]
933 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
953 ; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]]
955 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[DE]], [[ARGC]]
978 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
998 ; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]]
1000 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[DE]], [[ARGC]]
1023 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
1043 ; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[BC]], [[ARGC:%.*]]
1045 ; CHECK-NEXT:    [[AND2:%.*]] = and i32 [[DE]], [[ARGC]]
1064 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192
1080 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192
1096 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192
1112 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192
1128 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192
1144 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192
1160 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192
1176 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 192
1192 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896
1208 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896
1224 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896
1240 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896
1256 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896
1272 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896
1288 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896
1304 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 32896