Lines Matching refs:V1
14 ; CHECK-NOMEMSSA-NEXT: [[V1:%.*]] = load i32, ptr @G1, align 4
17 ; CHECK-NOMEMSSA-NEXT: [[DIFF:%.*]] = sub i32 [[V1]], [[V2]]
21 ; CHECK-NEXT: [[V1:%.*]] = load i32, ptr @G1, align 4
25 %V1 = load i32, ptr @G1
28 %Diff = sub i32 %V1, %V2
36 ; CHECK-NOMEMSSA-NEXT: [[V1:%.*]] = load i32, ptr @G1, align 4
38 ; CHECK-NOMEMSSA-NEXT: store i32 [[V1]], ptr @G1, align 4
43 ; CHECK-NEXT: [[V1:%.*]] = load i32, ptr @G1, align 4
48 %V1 = load i32, ptr @G1
50 store i32 %V1, ptr @G1
59 ; CHECK-NOMEMSSA-NEXT: [[V1:%.*]] = load i32, ptr @G1, align 4
66 ; CHECK-NOMEMSSA-NEXT: [[SUM:%.*]] = add i32 [[V1]], [[V2]]
72 ; CHECK-NEXT: [[V1:%.*]] = load i32, ptr @G1, align 4
78 ; CHECK-NEXT: [[SUM:%.*]] = add i32 [[V1]], [[V1]]
104 ; CHECK-NOMEMSSA-NEXT: [[V1:%.*]] = load i32, ptr @G1, align 4
105 ; CHECK-NOMEMSSA-NEXT: store i32 [[V1]], ptr @G2, align 4
117 ; CHECK-NEXT: [[V1:%.*]] = load i32, ptr @G1, align 4
118 ; CHECK-NEXT: store i32 [[V1]], ptr @G2, align 4
124 ; CHECK-NEXT: store i32 [[V1]], ptr @G3, align 4