Lines Matching refs:f3
68 @f3.i = internal thread_local unnamed_addr global i32 1, align 4
70 define dso_preemptable i32 @f3() nounwind {
72 ; PIC32-LABEL: f3:
74 ; PIC32: addiu $4, $[[R0]], %tlsldm(f3.i)
77 ; PIC32: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
79 ; PIC32: lw $[[R3:[0-9]+]], %dtprel_lo(f3.i)($[[R1]])
81 ; PIC32: sw $[[R3]], %dtprel_lo(f3.i)($[[R1]])
83 ; PIC64-LABEL: f3:
84 ; PIC64: lui $[[R0:[a-z0-9]+]], %hi(%neg(%gp_rel(f3)))
86 ; PIC64: daddiu $[[R1:[a-z0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f3)))
87 ; PIC64: daddiu $4, $[[R1]], %tlsldm(f3.i)
90 ; PIC64: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
92 ; PIC64: lw $[[R2:[0-9]+]], %dtprel_lo(f3.i)($[[R1]])
94 ; PIC64: sw $[[R2]], %dtprel_lo(f3.i)($[[R1]])
96 ; MM-LABEL: f3:
97 ; MM: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
99 ; MM: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
101 ; MM: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]])
103 %0 = load i32, i32* @f3.i, align 4
105 store i32 %inc, i32* @f3.i, align 4