Lines Matching refs:EB

2 …=mips32              -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s
4 …=mips32r2            -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s
6 …s32r6            -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32R6,MIPS32R6-EB %s
8 …4    -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s
10 …64   -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s
12 …r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64R2-EB %s
31 ; MIPS32-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
32 ; MIPS32-EB:     lwr $[[R0]], 3($[[R1]])
43 ; MIPS64-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
44 ; MIPS64-EB:     lwr $[[R0]], 3($[[R1]])
46 ; MIPS64R2-EB:   lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
47 ; MIPS64R2-EB:   lwr $[[R0]], 3($[[R1]])
63 ; MIPS32-EB:     swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
64 ; MIPS32-EB:     swr $[[R0]], 3($[[R1]])
75 ; MIPS64-EB:     swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
76 ; MIPS64-EB:     swr $[[R0]], 3($[[R1]])
78 ; MIPS64R2-EB:   swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
79 ; MIPS64R2-EB:   swr $[[R0]], 3($[[R1]])
97 ; MIPS32-EB:     lwl $2, 0($[[R1:[0-9]+]])
98 ; MIPS32-EB:     lwr $2, 3($[[R1]])
99 ; MIPS32-EB:     lwl $3, 4($[[R1:[0-9]+]])
100 ; MIPS32-EB:     lwr $3, 7($[[R1]])
112 ; MIPS64-EB:     ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
113 ; MIPS64-EB:     ldr $[[R0]], 7($[[R1]])
115 ; MIPS64R2-EB:   ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
116 ; MIPS64R2-EB:   ldr $[[R0]], 7($[[R1]])
132 ; MIPS32-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
133 ; MIPS32-EB:     lwr $[[R0]], 3($[[R1]])
138 ; MIPS32R6-EB:   lw $3, 0($[[PTR]])
139 ; MIPS32R6-EB:   sra $2, $3, 31
147 ; MIPS64-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
148 ; MIPS64-EB:     lwr $[[R0]], 3($[[R1]])
150 ; MIPS64R2-EB:   lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
151 ; MIPS64R2-EB:   lwr $[[R0]], 3($[[R1]])
169 ; MIPS32-EB-DAG: lwl $[[R2:3]], 0($[[R1:[0-9]+]])
170 ; MIPS32-EB-DAG: lwr $[[R2]],   3($[[R1]])
171 ; MIPS32-EB-DAG: addiu $2, $zero, 0
176 ; MIPS32R6-EB-DAG: lw $3, 0($[[PTR]])
177 ; MIPS32R6-EB-DAG: addiu $2, $zero, 0
190 ; MIPS64-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
191 ; MIPS64-EB:     lwr $[[R0]], 3($[[R1]])
193 ; MIPS64R2-EB:   lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
194 ; MIPS64R2-EB:   lwr $[[R0]], 3($[[R1]])
195 ; MIPS64R2-EB:   dext $[[R0]], $[[R0]], 0, 32
214 ; MIPS32-EB-DAG: swl $[[A1:4]], 0($[[R1:[0-9]+]])
215 ; MIPS32-EB-DAG: swr $[[A1]],   3($[[R1]])
216 ; MIPS32-EB-DAG: swl $[[A1:5]], 4($[[R1:[0-9]+]])
217 ; MIPS32-EB-DAG: swr $[[A1]],   7($[[R1]])
229 ; MIPS64-EB:     sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
230 ; MIPS64-EB:     sdr $[[R0]], 7($[[R1]])
232 ; MIPS64R2-EB:   sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
233 ; MIPS64R2-EB:   sdr $[[R0]], 7($[[R1]])
249 ; MIPS32-EB:     swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
250 ; MIPS32-EB:     swr $[[R0]], 3($[[R1]])
261 ; MIPS64-EB:     swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
262 ; MIPS64-EB:     swr $[[R0]], 3($[[R1]])
264 ; MIPS64R2-EB:   swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
265 ; MIPS64R2-EB:   swr $[[R0]], 3($[[R1]])
291 ; MIPS32-EB:     lw $[[PTR:[0-9]+]], %got(struct_s0)(
295 ; MIPS64-EB:     ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
296 ; MIPS64R2-EB:   ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(
322 ; MIPS32-EB:     lw $[[PTR:[0-9]+]], %got(struct_s1)(
327 ; MIPS32-EB-DAG:    lwl $[[R1:[0-9]+]], 0($[[PTR]])
328 ; MIPS32-EB-DAG:    lwr $[[R1]], 3($[[PTR]])
329 ; MIPS32-EB-DAG:    swl $[[R1]], 4($[[PTR]])
330 ; MIPS32-EB-DAG:    swr $[[R1]], 7($[[PTR]])
347 ; MIPS64-EB:     ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
348 ; MIPS64R2-EB:   ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(
360 ; MIPS64-EB-DAG:    lwl $[[R1:[0-9]+]], 0($[[PTR]])
361 ; MIPS64-EB-DAG:    lwr $[[R1]], 3($[[PTR]])
362 ; MIPS64-EB-DAG:    swl $[[R1]], 4($[[PTR]])
363 ; MIPS64-EB-DAG:    swr $[[R1]], 7($[[PTR]])
365 ; MIPS64R2-EB-DAG:    lwl $[[R1:[0-9]+]], 0($[[PTR]])
366 ; MIPS64R2-EB-DAG:    lwr $[[R1]], 3($[[PTR]])
367 ; MIPS64R2-EB-DAG:    swl $[[R1]], 4($[[PTR]])
368 ; MIPS64R2-EB-DAG:    swr $[[R1]], 7($[[PTR]])
402 ; MIPS32-EB:     lw $[[PTR:[0-9]+]], %got(struct_s2)(
403 ; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])
404 ; MIPS32-EB-DAG: lwr $[[R1]],        3($[[PTR]])
405 ; MIPS32-EB-DAG: swl $[[R1]],        8($[[PTR]])
406 ; MIPS32-EB-DAG: swr $[[R1]],       11($[[PTR]])
407 ; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 4($[[PTR]])
408 ; MIPS32-EB-DAG: lwr $[[R1]],        7($[[PTR]])
409 ; MIPS32-EB-DAG: swl $[[R1]],       12($[[PTR]])
410 ; MIPS32-EB-DAG: swr $[[R1]],       15($[[PTR]])
432 ; MIPS64-EB:     ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
433 ; MIPS64-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]])
434 ; MIPS64-EB-DAG: ldr $[[R1]],        7($[[PTR]])
435 ; MIPS64-EB-DAG: sdl $[[R1]],        8($[[PTR]])
436 ; MIPS64-EB-DAG: sdr $[[R1]],       15($[[PTR]])
438 ; MIPS64R2-EB:     ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(
439 ; MIPS64R2-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]])
440 ; MIPS64R2-EB-DAG: ldr $[[R1]],        7($[[PTR]])
441 ; MIPS64R2-EB-DAG: sdl $[[R1]],        8($[[PTR]])
442 ; MIPS64R2-EB-DAG: sdr $[[R1]],       15($[[PTR]])
475 ; MIPS32-EB:     lw $[[SPTR:[0-9]+]], %got(arr)(
476 ; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[PTR]])
477 ; MIPS32-EB-DAG: lwr $[[R1]],   3($[[PTR]])
478 ; MIPS32-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]])
479 ; MIPS32-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]])
480 ; MIPS32-EB-DAG: sll $[[T0:[0-9]+]], $[[R3]], 8
481 ; MIPS32-EB-DAG: or  $[[T1:[0-9]+]], $[[T0]], $[[R2]]
482 ; MIPS32-EB-DAG: sll $[[T1]], $[[T1]], 16
483 ; MIPS32-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]])
484 ; MIPS32-EB-DAG: sll $[[T2:[0-9]+]], $[[R4]], 8
485 ; MIPS32-EB-DAG: or  $5, $[[T1]], $[[T2]]
494 ; MIPS32R6-EB-DAG: lhu $[[R2:[0-9]+]], 4($[[PTR]])
495 ; MIPS32R6-EB-DAG: lbu $[[R3:[0-9]+]], 6($[[PTR]])
496 ; MIPS32R6-EB-DAG: sll $[[T0:[0-9]+]], $[[R2]], 16
497 ; MIPS32R6-EB-DAG: or  $5, $[[T0]], $[[R3]]
507 ; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
508 ; MIPS64-EB-DAG: lbu  $[[R2:[0-9]+]], 5($[[PTR]])
509 ; MIPS64-EB-DAG: lbu  $[[R3:[0-9]+]], 4($[[PTR]])
510 ; MIPS64-EB-DAG: dsll $[[T0:[0-9]+]], $[[R3]], 8
511 ; MIPS64-EB-DAG: or   $[[T1:[0-9]+]], $[[T0]], $[[R2]]
512 ; MIPS64-EB-DAG: lbu  $[[R4:[0-9]+]], 6($[[PTR]])
513 ; MIPS64-EB-DAG: dsll $[[T1]], $[[T1]], 16
514 ; MIPS64-EB-DAG: lwl  $[[R1:[0-9]+]], 0($[[PTR]])
515 ; MIPS64-EB-DAG: lwr  $[[R1]],   3($[[PTR]])
516 ; MIPS64-EB-DAG: dsll $[[R5:[0-9]+]], $[[R1]], 32
517 ; MIPS64-EB-DAG: or   $[[T3:[0-9]+]], $[[R5]], $[[T1]]
518 ; MIPS64-EB-DAG: dsll $[[T4:[0-9]+]], $[[R4]], 8
519 ; MIPS64-EB-DAG: or   $4, $[[T3]], $[[T4]]
521 ; MIPS64R2-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)(
522 ; MIPS64R2-EB-DAG: lbu  $[[R1:[0-9]+]], 5($[[PTR]])
523 ; MIPS64R2-EB-DAG: lbu  $[[R2:[0-9]+]], 4($[[PTR]])
524 ; MIPS64R2-EB-DAG: dsll $[[T0:[0-9]+]], $[[R2]], 8
525 ; MIPS64R2-EB-DAG: or   $[[T1:[0-9]+]], $[[T0]], $[[R1]]
526 ; MIPS64R2-EB-DAG: dsll $[[T1]], $[[T1]], 16
527 ; MIPS64R2-EB-DAG: lwl  $[[R3:[0-9]+]], 0($[[PTR]])
528 ; MIPS64R2-EB-DAG: lwr  $[[R3]], 3($[[PTR]])
529 ; MIPS64R2-EB-DAG: dext $[[R3]], $[[R3]], 0, 32
530 ; MIPS64R2-EB-DAG: dsll $[[R3]], $[[R3]], 32
531 ; MIPS64R2-EB-DAG: or   $[[T2:[0-9]+]], $[[R3]], $[[T1]]
532 ; MIPS64R2-EB-DAG: lbu  $[[R4:[0-9]+]], 6($[[PTR]])
533 ; MIPS64R2-EB-DAG: dsll $[[T3:[0-9]+]], $[[R4]], 8
534 ; MIPS64R2-EB-DAG: or   $4, $[[T2]], $[[T3]]