Lines Matching refs:f0
41 ; M2-NEXT: ldc1 $f0, 16($sp)
45 ; M2-NEXT: mtc1 $7, $f0
54 ; CMOV32R1-NEXT: ldc1 $f0, 16($sp)
56 ; CMOV32R1-NEXT: movn.d $f0, $f2, $1
63 ; CMOV32R2-NEXT: ldc1 $f0, 16($sp)
65 ; CMOV32R2-NEXT: movn.d $f0, $f2, $1
71 ; 32R6-NEXT: mtc1 $4, $f0
74 ; 32R6-NEXT: sel.d $f0, $f2, $f1
80 ; M3-NEXT: mov.d $f0, $f13
82 ; M3-NEXT: mov.d $f0, $f14
89 ; CMOV64-NEXT: mov.d $f0, $f14
92 ; CMOV64-NEXT: movn.d $f0, $f13, $1
96 ; 64R6-NEXT: mtc1 $4, $f0
98 ; 64R6-NEXT: sel.d $f0, $f14, $f13
105 ; MM32R3: ldc1 $f0, 16($sp) # <MCInst #{{.*}} LDC1_MM
107 ; MM32R3: movn.d $f0, $f2, $2 # <MCInst #{{.*}} MOVN_I_D32_MM
113 ; MM32R6-NEXT: mtc1 $4, $f0
115 ; MM32R6-NEXT: sel.d $f0, $f2, $f1
128 ; M2-NEXT: mov.d $f0, $f12
130 ; M2-NEXT: mov.d $f0, $f14
137 ; CMOV32R1-NEXT: mov.d $f0, $f14
141 ; CMOV32R1-NEXT: movn.d $f0, $f12, $1
145 ; CMOV32R2-NEXT: mov.d $f0, $f14
149 ; CMOV32R2-NEXT: movn.d $f0, $f12, $1
154 ; 32R6-NEXT: mtc1 $1, $f0
156 ; 32R6-NEXT: sel.d $f0, $f14, $f12
162 ; M3-NEXT: mov.d $f0, $f12
164 ; M3-NEXT: mov.d $f0, $f13
171 ; CMOV64-NEXT: mov.d $f0, $f13
174 ; CMOV64-NEXT: movn.d $f0, $f12, $1
178 ; 64R6-NEXT: mtc1 $6, $f0
180 ; 64R6-NEXT: sel.d $f0, $f13, $f12
184 ; MM32R3: mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
188 ; MM32R3: movn.d $f0, $f12, $2 # <MCInst #{{.*}} MOVN_I_D32_MM
193 ; MM32R6-NEXT: mtc1 $1, $f0
194 ; MM32R6-NEXT: sel.d $f0, $f14, $f12
208 ; M2-NEXT: mov.d $f0, $f12
210 ; M2-NEXT: mov.d $f0, $f14
217 ; CMOV32R1-NEXT: mov.d $f0, $f14
220 ; CMOV32R1-NEXT: movt.d $f0, $f12, $fcc0
224 ; CMOV32R2-NEXT: mov.d $f0, $f14
227 ; CMOV32R2-NEXT: movt.d $f0, $f12, $fcc0
231 ; 32R6-NEXT: cmp.lt.d $f0, $f12, $f14
232 ; 32R6-NEXT: mfc1 $1, $f0
233 ; 32R6-NEXT: mtc1 $1, $f0
235 ; 32R6-NEXT: sel.d $f0, $f14, $f12
242 ; M3-NEXT: mov.d $f0, $f12
244 ; M3-NEXT: mov.d $f0, $f13
251 ; CMOV64-NEXT: mov.d $f0, $f13
254 ; CMOV64-NEXT: movt.d $f0, $f12, $fcc0
258 ; 64R6-NEXT: cmp.lt.d $f0, $f12, $f13
259 ; 64R6-NEXT: mfc1 $1, $f0
260 ; 64R6-NEXT: mtc1 $1, $f0
262 ; 64R6-NEXT: sel.d $f0, $f13, $f12
266 ; MM32R3: mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
269 ; MM32R3: movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
273 ; MM32R6-NEXT: cmp.lt.d $f0, $f12, $f14
274 ; MM32R6-NEXT: mfc1 $1, $f0
275 ; MM32R6-NEXT: mtc1 $1, $f0
276 ; MM32R6-NEXT: sel.d $f0, $f14, $f12
290 ; M2-NEXT: mov.d $f0, $f12
292 ; M2-NEXT: mov.d $f0, $f14
299 ; CMOV32R1-NEXT: mov.d $f0, $f14
302 ; CMOV32R1-NEXT: movt.d $f0, $f12, $fcc0
306 ; CMOV32R2-NEXT: mov.d $f0, $f14
309 ; CMOV32R2-NEXT: movt.d $f0, $f12, $fcc0
313 ; 32R6-NEXT: cmp.le.d $f0, $f12, $f14
314 ; 32R6-NEXT: mfc1 $1, $f0
315 ; 32R6-NEXT: mtc1 $1, $f0
317 ; 32R6-NEXT: sel.d $f0, $f14, $f12
324 ; M3-NEXT: mov.d $f0, $f12
326 ; M3-NEXT: mov.d $f0, $f13
333 ; CMOV64-NEXT: mov.d $f0, $f13
336 ; CMOV64-NEXT: movt.d $f0, $f12, $fcc0
340 ; 64R6-NEXT: cmp.le.d $f0, $f12, $f13
341 ; 64R6-NEXT: mfc1 $1, $f0
342 ; 64R6-NEXT: mtc1 $1, $f0
344 ; 64R6-NEXT: sel.d $f0, $f13, $f12
348 ; MM32R3: mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
351 ; MM32R3: movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
355 ; MM32R6-NEXT: cmp.le.d $f0, $f12, $f14
356 ; MM32R6-NEXT: mfc1 $1, $f0
357 ; MM32R6-NEXT: mtc1 $1, $f0
358 ; MM32R6-NEXT: sel.d $f0, $f14, $f12
372 ; M2-NEXT: mov.d $f0, $f12
374 ; M2-NEXT: mov.d $f0, $f14
381 ; CMOV32R1-NEXT: mov.d $f0, $f14
384 ; CMOV32R1-NEXT: movf.d $f0, $f12, $fcc0
388 ; CMOV32R2-NEXT: mov.d $f0, $f14
391 ; CMOV32R2-NEXT: movf.d $f0, $f12, $fcc0
395 ; 32R6-NEXT: cmp.lt.d $f0, $f14, $f12
396 ; 32R6-NEXT: mfc1 $1, $f0
397 ; 32R6-NEXT: mtc1 $1, $f0
399 ; 32R6-NEXT: sel.d $f0, $f14, $f12
406 ; M3-NEXT: mov.d $f0, $f12
408 ; M3-NEXT: mov.d $f0, $f13
415 ; CMOV64-NEXT: mov.d $f0, $f13
418 ; CMOV64-NEXT: movf.d $f0, $f12, $fcc0
422 ; 64R6-NEXT: cmp.lt.d $f0, $f13, $f12
423 ; 64R6-NEXT: mfc1 $1, $f0
424 ; 64R6-NEXT: mtc1 $1, $f0
426 ; 64R6-NEXT: sel.d $f0, $f13, $f12
430 ; MM32R3: mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
433 ; MM32R3: movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
437 ; MM32R6-NEXT: cmp.lt.d $f0, $f14, $f12
438 ; MM32R6-NEXT: mfc1 $1, $f0
439 ; MM32R6-NEXT: mtc1 $1, $f0
440 ; MM32R6-NEXT: sel.d $f0, $f14, $f12
454 ; M2-NEXT: mov.d $f0, $f12
456 ; M2-NEXT: mov.d $f0, $f14
463 ; CMOV32R1-NEXT: mov.d $f0, $f14
466 ; CMOV32R1-NEXT: movf.d $f0, $f12, $fcc0
470 ; CMOV32R2-NEXT: mov.d $f0, $f14
473 ; CMOV32R2-NEXT: movf.d $f0, $f12, $fcc0
477 ; 32R6-NEXT: cmp.le.d $f0, $f14, $f12
478 ; 32R6-NEXT: mfc1 $1, $f0
479 ; 32R6-NEXT: mtc1 $1, $f0
481 ; 32R6-NEXT: sel.d $f0, $f14, $f12
488 ; M3-NEXT: mov.d $f0, $f12
490 ; M3-NEXT: mov.d $f0, $f13
497 ; CMOV64-NEXT: mov.d $f0, $f13
500 ; CMOV64-NEXT: movf.d $f0, $f12, $fcc0
504 ; 64R6-NEXT: cmp.le.d $f0, $f13, $f12
505 ; 64R6-NEXT: mfc1 $1, $f0
506 ; 64R6-NEXT: mtc1 $1, $f0
508 ; 64R6-NEXT: sel.d $f0, $f13, $f12
512 ; MM32R3: mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
515 ; MM32R3: movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
519 ; MM32R6-NEXT: cmp.le.d $f0, $f14, $f12
520 ; MM32R6-NEXT: mfc1 $1, $f0
521 ; MM32R6-NEXT: mtc1 $1, $f0
522 ; MM32R6-NEXT: sel.d $f0, $f14, $f12
536 ; M2-NEXT: mov.d $f0, $f12
538 ; M2-NEXT: mov.d $f0, $f14
545 ; CMOV32R1-NEXT: mov.d $f0, $f14
548 ; CMOV32R1-NEXT: movt.d $f0, $f12, $fcc0
552 ; CMOV32R2-NEXT: mov.d $f0, $f14
555 ; CMOV32R2-NEXT: movt.d $f0, $f12, $fcc0
559 ; 32R6-NEXT: cmp.eq.d $f0, $f12, $f14
560 ; 32R6-NEXT: mfc1 $1, $f0
561 ; 32R6-NEXT: mtc1 $1, $f0
563 ; 32R6-NEXT: sel.d $f0, $f14, $f12
570 ; M3-NEXT: mov.d $f0, $f12
572 ; M3-NEXT: mov.d $f0, $f13
579 ; CMOV64-NEXT: mov.d $f0, $f13
582 ; CMOV64-NEXT: movt.d $f0, $f12, $fcc0
586 ; 64R6-NEXT: cmp.eq.d $f0, $f12, $f13
587 ; 64R6-NEXT: mfc1 $1, $f0
588 ; 64R6-NEXT: mtc1 $1, $f0
590 ; 64R6-NEXT: sel.d $f0, $f13, $f12
594 ; MM32R3: mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
597 ; MM32R3: movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
601 ; MM32R6-NEXT: cmp.eq.d $f0, $f12, $f14
602 ; MM32R6-NEXT: mfc1 $1, $f0
603 ; MM32R6-NEXT: mtc1 $1, $f0
604 ; MM32R6-NEXT: sel.d $f0, $f14, $f12
618 ; M2-NEXT: mov.d $f0, $f12
620 ; M2-NEXT: mov.d $f0, $f14
627 ; CMOV32R1-NEXT: mov.d $f0, $f14
630 ; CMOV32R1-NEXT: movf.d $f0, $f12, $fcc0
634 ; CMOV32R2-NEXT: mov.d $f0, $f14
637 ; CMOV32R2-NEXT: movf.d $f0, $f12, $fcc0
641 ; 32R6-NEXT: cmp.ueq.d $f0, $f12, $f14
642 ; 32R6-NEXT: mfc1 $1, $f0
644 ; 32R6-NEXT: mtc1 $1, $f0
646 ; 32R6-NEXT: sel.d $f0, $f14, $f12
653 ; M3-NEXT: mov.d $f0, $f12
655 ; M3-NEXT: mov.d $f0, $f13
662 ; CMOV64-NEXT: mov.d $f0, $f13
665 ; CMOV64-NEXT: movf.d $f0, $f12, $fcc0
669 ; 64R6-NEXT: cmp.ueq.d $f0, $f12, $f13
670 ; 64R6-NEXT: mfc1 $1, $f0
672 ; 64R6-NEXT: mtc1 $1, $f0
674 ; 64R6-NEXT: sel.d $f0, $f13, $f12
678 ; MM32R3: mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
681 ; MM32R3: movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
685 ; MM32R6-NEXT: cmp.ueq.d $f0, $f12, $f14
686 ; MM32R6-NEXT: mfc1 $1, $f0
688 ; MM32R6-NEXT: mtc1 $1, $f0
689 ; MM32R6-NEXT: sel.d $f0, $f14, $f12