Lines Matching refs:R2
11 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-F…
12 …march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A
13 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO…
14 …rch=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A
31 ; 32R2-NO-FP64A-LE-NOT: addiu $sp, $sp
32 ; 32R2-NO-FP64A-LE: mtc1 $4, $f0
33 ; 32R2-NO-FP64A-LE: mthc1 $5, $f0
35 ; 32R2-NO-FP64A-BE-NOT: addiu $sp, $sp
36 ; 32R2-NO-FP64A-BE: mtc1 $5, $f0
37 ; 32R2-NO-FP64A-BE: mthc1 $4, $f0
39 ; 32R2-FP64A: addiu $sp, $sp, -8
40 ; 32R2-FP64A: sw $4, 0($sp)
41 ; 32R2-FP64A: sw $5, 4($sp)
42 ; 32R2-FP64A: ldc1 $f0, 0($sp)
53 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0
54 ; 32R2-NO-FP64A-LE: mthc1 $7, $f0
56 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0
57 ; 32R2-NO-FP64A-BE: mthc1 $6, $f0
59 ; 32R2-FP64A: addiu $sp, $sp, -8
60 ; 32R2-FP64A: sw $6, 0($sp)
61 ; 32R2-FP64A: sw $7, 4($sp)
62 ; 32R2-FP64A: ldc1 $f0, 0($sp)
73 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0
74 ; 32R2-NO-FP64A-LE: mthc1 $7, $f0
76 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0
77 ; 32R2-NO-FP64A-BE: mthc1 $6, $f0
79 ; 32R2-FP64A: addiu $sp, $sp, -8
80 ; 32R2-FP64A: sw $6, 0($sp)
81 ; 32R2-FP64A: sw $7, 4($sp)
82 ; 32R2-FP64A: ldc1 $f0, 0($sp)
93 ; 32R2-NO-FP64A-LE: mtc1 $6, $f0
94 ; 32R2-NO-FP64A-LE: mthc1 $7, $f0
96 ; 32R2-NO-FP64A-BE: mtc1 $7, $f0
97 ; 32R2-NO-FP64A-BE: mthc1 $6, $f0
99 ; 32R2-FP64A: addiu $sp, $sp, -8
100 ; 32R2-FP64A: sw $6, 0($sp)
101 ; 32R2-FP64A: sw $7, 4($sp)
102 ; 32R2-FP64A: ldc1 $f0, 0($sp)
114 ; 32R2-NO-FP64A-LE-DAG: mtc1 $4, $[[T0:f[0-9]+]]
115 ; 32R2-NO-FP64A-LE-DAG: mthc1 $5, $[[T0:f[0-9]+]]
116 ; 32R2-NO-FP64A-LE-DAG: mtc1 $6, $[[T1:f[0-9]+]]
117 ; 32R2-NO-FP64A-LE-DAG: mthc1 $7, $[[T1:f[0-9]+]]
118 ; 32R2-NO-FP64A-LE: sub.d $f0, $[[T0]], $[[T1]]
120 ; 32R2-NO-FP64A-BE-DAG: mtc1 $5, $[[T0:f[0-9]+]]
121 ; 32R2-NO-FP64A-BE-DAG: mthc1 $4, $[[T0:f[0-9]+]]
122 ; 32R2-NO-FP64A-BE-DAG: mtc1 $7, $[[T1:f[0-9]+]]
123 ; 32R2-NO-FP64A-BE-DAG: mthc1 $6, $[[T1:f[0-9]+]]
124 ; 32R2-NO-FP64A-BE: sub.d $f0, $[[T0]], $[[T1]]
126 ; 32R2-FP64A: addiu $sp, $sp, -8
127 ; 32R2-FP64A: sw $6, 0($sp)
128 ; 32R2-FP64A: sw $7, 4($sp)
129 ; 32R2-FP64A: ldc1 $[[T1:f[0-9]+]], 0($sp)
130 ; 32R2-FP64A: sw $4, 0($sp)
131 ; 32R2-FP64A: sw $5, 4($sp)
132 ; 32R2-FP64A: ldc1 $[[T0:f[0-9]+]], 0($sp)
133 ; 32R2-FP64A: sub.d $f0, $[[T0]], $[[T1]]
145 ; 32R2-NO-FP64A-LE-DAG: mfc1 $6, $f0
146 ; 32R2-NO-FP64A-LE-DAG: mfhc1 $7, $f0
148 ; 32R2-NO-FP64A-BE-DAG: mfc1 $7, $f0
149 ; 32R2-NO-FP64A-BE-DAG: mfhc1 $6, $f0
151 ; 32R2-FP64A: addiu $sp, $sp, -32
152 ; 32R2-FP64A: sdc1 $f0, 16($sp)
153 ; 32R2-FP64A: lw $6, 16($sp)
155 ; 32R2-FP64A: sdc1 $f0, 16($sp)
156 ; 32R2-FP64A: lw $7, 20($sp)