Lines Matching refs:R2
9 …mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN
12 …mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN
15 …llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN
18 … %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN
42 ; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
43 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
44 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
45 ; 32R2: add.s $f0, $[[T1]], $[[T2]]
57 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
58 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
59 ; 64R2: add.s $f0, $[[T0]], $[[T1]]
82 ; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
83 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
84 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
85 ; 32R2: add.s $f0, $[[T1]], $[[T2]]
97 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
98 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
99 ; 64R2: add.s $f0, $[[T0]], $[[T1]]
122 ; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
123 ; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
125 ; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
126 ; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
127 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
128 ; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
142 ; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
144 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
145 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
146 ; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
169 ; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
170 ; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14
172 ; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
173 ; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
174 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
175 ; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
183 ; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
184 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
185 ; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
208 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
209 ; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
210 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
211 ; 32R2: mthc1 $zero, $[[T2]]
212 ; 32R2: add.d $f0, $[[T1]], $[[T2]]
224 ; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
225 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
226 ; 64R2: add.d $f0, $[[T0]], $[[T1]]
249 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
250 ; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
251 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
252 ; 32R2: mthc1 $zero, $[[T2]]
253 ; 32R2: add.d $f0, $[[T1]], $[[T2]]
265 ; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
266 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
267 ; 64R2: add.d $f0, $[[T0]], $[[T1]]
290 ; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
291 ; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14
293 ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
294 ; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
295 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
296 ; 32R2-NAN: mthc1 $zero, $[[T2]]
297 ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
311 ; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
313 ; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
314 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
315 ; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
338 ; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
339 ; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14
341 ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
342 ; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
343 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
344 ; 32R2-NAN: mthc1 $zero, $[[T2]]
345 ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
359 ; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13
361 ; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
362 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
363 ; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]