Lines Matching refs:tmp2
7 %tmp2 = load <8 x i8>, <8 x i8>* %B
8 %tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
17 %tmp2 = load <4 x i16>, <4 x i16>* %B
18 %tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
27 %tmp2 = load <2 x i32>, <2 x i32>* %B
28 %tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 >
37 %tmp2 = load <1 x i64>, <1 x i64>* %B
38 %tmp3 = ashr <1 x i64> %tmp2, < i64 63 >
47 %tmp2 = load <16 x i8>, <16 x i8>* %B
48 …%tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, …
57 %tmp2 = load <8 x i16>, <8 x i16>* %B
58 %tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
67 %tmp2 = load <4 x i32>, <4 x i32>* %B
68 %tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
77 %tmp2 = load <2 x i64>, <2 x i64>* %B
78 %tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 >
87 %tmp2 = load <8 x i8>, <8 x i8>* %B
88 %tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
97 %tmp2 = load <4 x i16>, <4 x i16>* %B
98 %tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
107 %tmp2 = load <2 x i32>, <2 x i32>* %B
108 %tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 >
117 %tmp2 = load <1 x i64>, <1 x i64>* %B
118 %tmp3 = lshr <1 x i64> %tmp2, < i64 63 >
127 %tmp2 = load <16 x i8>, <16 x i8>* %B
128 …%tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, …
137 %tmp2 = load <8 x i16>, <8 x i16>* %B
138 %tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
147 %tmp2 = load <4 x i32>, <4 x i32>* %B
148 %tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
157 %tmp2 = load <2 x i64>, <2 x i64>* %B
158 %tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 >
167 %tmp2 = load <8 x i8>, <8 x i8>* %B
168 …%tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8,…
177 %tmp2 = load <4 x i16>, <4 x i16>* %B
178 …%tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16…
187 %tmp2 = load <2 x i32>, <2 x i32>* %B
188 …%tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32…
197 %tmp2 = load <1 x i64>, <1 x i64>* %B
198 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
207 %tmp2 = load <8 x i8>, <8 x i8>* %B
208 …%tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8,…
217 %tmp2 = load <4 x i16>, <4 x i16>* %B
218 …%tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16…
227 %tmp2 = load <2 x i32>, <2 x i32>* %B
228 …%tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32…
237 %tmp2 = load <1 x i64>, <1 x i64>* %B
238 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
247 %tmp2 = load <16 x i8>, <16 x i8>* %B
248 …%tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8…
257 %tmp2 = load <8 x i16>, <8 x i16>* %B
258 …%tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16…
267 %tmp2 = load <4 x i32>, <4 x i32>* %B
268 …%tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32…
277 %tmp2 = load <2 x i64>, <2 x i64>* %B
278 …%tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64…
287 %tmp2 = load <16 x i8>, <16 x i8>* %B
288 …%tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8…
297 %tmp2 = load <8 x i16>, <8 x i16>* %B
298 …%tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16…
307 %tmp2 = load <4 x i32>, <4 x i32>* %B
308 …%tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32…
317 %tmp2 = load <2 x i64>, <2 x i64>* %B
318 …%tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64…