Lines Matching refs:k5
20 ; CHECK: %llvm.amdgcn.kernel.k5.lds.t = type { [20 x i8], [12 x i8], [19 x i8], [13 x i8], [18 x i8…
27 ; CHECK: @llvm.amdgcn.kernel.k5.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k5.lds.t und…
170 ; CHECK-NOT: @k5.lds.size.17.align.16
171 ; CHECK-NOT: @k5.lds.size.18.align.16
172 ; CHECK-NOT: @k5.lds.size.19.align.16
173 ; CHECK-NOT: @k5.lds.size.20.align.16
174 @k5.lds.size.17.align.16 = internal unnamed_addr addrspace(3) global [17 x i8] undef, align 16
175 @k5.lds.size.18.align.16 = internal unnamed_addr addrspace(3) global [18 x i8] undef, align 16
176 @k5.lds.size.19.align.16 = internal unnamed_addr addrspace(3) global [19 x i8] undef, align 16
177 @k5.lds.size.20.align.16 = internal unnamed_addr addrspace(3) global [20 x i8] undef, align 16
179 define amdgpu_kernel void @k5() {
180 …%k5.lds.size.17.align.16.bc = bitcast [17 x i8] addrspace(3)* @k5.lds.size.17.align.16 to i8 addrs…
181 store i8 1, i8 addrspace(3)* %k5.lds.size.17.align.16.bc, align 16
183 …%k5.lds.size.18.align.16.bc = bitcast [18 x i8] addrspace(3)* @k5.lds.size.18.align.16 to i8 addrs…
184 store i8 2, i8 addrspace(3)* %k5.lds.size.18.align.16.bc, align 16
186 …%k5.lds.size.19.align.16.bc = bitcast [19 x i8] addrspace(3)* @k5.lds.size.19.align.16 to i8 addrs…
187 store i8 3, i8 addrspace(3)* %k5.lds.size.19.align.16.bc, align 16
189 …%k5.lds.size.20.align.16.bc = bitcast [20 x i8] addrspace(3)* @k5.lds.size.20.align.16 to i8 addrs…
190 store i8 4, i8 addrspace(3)* %k5.lds.size.20.align.16.bc, align 16