Lines Matching refs:EG

4 …dgpu-scalarize-global-loads=false  -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG
40 ; EG-LABEL: lshr_i32:
41 ; EG:       ; %bb.0:
42 ; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
43 ; EG-NEXT:    TEX 0 @6
44 ; EG-NEXT:    ALU 2, @9, KC0[CB0:0-32], KC1[]
45 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
46 ; EG-NEXT:    CF_END
47 ; EG-NEXT:    PAD
48 ; EG-NEXT:    Fetch clause starting at 6:
49 ; EG-NEXT:     VTX_READ_64 T0.XY, T0.X, 0, #1
50 ; EG-NEXT:    ALU clause starting at 8:
51 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
52 ; EG-NEXT:    ALU clause starting at 9:
53 ; EG-NEXT:     LSHR T0.X, T0.X, T0.Y,
54 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
55 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
99 ; EG-LABEL: lshr_v2i32:
100 ; EG:       ; %bb.0:
101 ; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
102 ; EG-NEXT:    TEX 0 @6
103 ; EG-NEXT:    ALU 3, @9, KC0[CB0:0-32], KC1[]
104 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
105 ; EG-NEXT:    CF_END
106 ; EG-NEXT:    PAD
107 ; EG-NEXT:    Fetch clause starting at 6:
108 ; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
109 ; EG-NEXT:    ALU clause starting at 8:
110 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
111 ; EG-NEXT:    ALU clause starting at 9:
112 ; EG-NEXT:     LSHR * T0.Y, T0.Y, T0.W,
113 ; EG-NEXT:     LSHR T0.X, T0.X, T0.Z,
114 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
115 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
166 ; EG-LABEL: lshr_v4i32:
167 ; EG:       ; %bb.0:
168 ; EG-NEXT:    ALU 0, @10, KC0[CB0:0-32], KC1[]
169 ; EG-NEXT:    TEX 1 @6
170 ; EG-NEXT:    ALU 5, @11, KC0[CB0:0-32], KC1[]
171 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
172 ; EG-NEXT:    CF_END
173 ; EG-NEXT:    PAD
174 ; EG-NEXT:    Fetch clause starting at 6:
175 ; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 16, #1
176 ; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
177 ; EG-NEXT:    ALU clause starting at 10:
178 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
179 ; EG-NEXT:    ALU clause starting at 11:
180 ; EG-NEXT:     LSHR * T0.W, T0.W, T1.W,
181 ; EG-NEXT:     LSHR * T0.Z, T0.Z, T1.Z,
182 ; EG-NEXT:     LSHR * T0.Y, T0.Y, T1.Y,
183 ; EG-NEXT:     LSHR T0.X, T0.X, T1.X,
184 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
185 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
227 ; EG-LABEL: lshr_i64:
228 ; EG:       ; %bb.0:
229 ; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
230 ; EG-NEXT:    TEX 0 @6
231 ; EG-NEXT:    ALU 9, @9, KC0[CB0:0-32], KC1[]
232 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
233 ; EG-NEXT:    CF_END
234 ; EG-NEXT:    PAD
235 ; EG-NEXT:    Fetch clause starting at 6:
236 ; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
237 ; EG-NEXT:    ALU clause starting at 8:
238 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
239 ; EG-NEXT:    ALU clause starting at 9:
240 ; EG-NEXT:     AND_INT * T0.W, T0.Z, literal.x,
241 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
242 ; EG-NEXT:     LSHR T1.Z, T0.Y, PV.W,
243 ; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.Y, T0.X, T0.Z,
244 ; EG-NEXT:     AND_INT * T1.W, T0.Z, literal.x,
245 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
246 ; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, PV.Z,
247 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
248 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
249 ; EG-NEXT:     CNDE_INT * T0.Y, T1.W, T1.Z, 0.0,
310 ; EG-LABEL: lshr_v4i64:
311 ; EG:       ; %bb.0:
312 ; EG-NEXT:    ALU 0, @14, KC0[CB0:0-32], KC1[]
313 ; EG-NEXT:    TEX 3 @6
314 ; EG-NEXT:    ALU 34, @15, KC0[CB0:0-32], KC1[]
315 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 0
316 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
317 ; EG-NEXT:    CF_END
318 ; EG-NEXT:    Fetch clause starting at 6:
319 ; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 32, #1
320 ; EG-NEXT:     VTX_READ_128 T2.XYZW, T0.X, 16, #1
321 ; EG-NEXT:     VTX_READ_128 T3.XYZW, T0.X, 48, #1
322 ; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
323 ; EG-NEXT:    ALU clause starting at 14:
324 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
325 ; EG-NEXT:    ALU clause starting at 15:
326 ; EG-NEXT:     AND_INT * T1.W, T1.Z, literal.x,
327 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
328 ; EG-NEXT:     LSHR T4.Z, T0.W, PV.W,
329 ; EG-NEXT:     AND_INT T1.W, T1.Z, literal.x,
330 ; EG-NEXT:     AND_INT * T3.W, T3.Z, literal.y,
331 ; EG-NEXT:    32(4.484155e-44), 31(4.344025e-44)
332 ; EG-NEXT:     BIT_ALIGN_INT T4.X, T0.W, T0.Z, T1.Z,
333 ; EG-NEXT:     LSHR T1.Y, T2.W, PS, BS:VEC_120/SCL_212
334 ; EG-NEXT:     AND_INT * T0.Z, T3.Z, literal.x,
335 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
336 ; EG-NEXT:     BIT_ALIGN_INT T0.W, T2.W, T2.Z, T3.Z,
337 ; EG-NEXT:     AND_INT * T2.W, T3.X, literal.x,
338 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
339 ; EG-NEXT:     AND_INT T5.X, T1.X, literal.x,
340 ; EG-NEXT:     LSHR T3.Y, T2.Y, PS,
341 ; EG-NEXT:     CNDE_INT T2.Z, T0.Z, PV.W, T1.Y,
342 ; EG-NEXT:     BIT_ALIGN_INT T0.W, T2.Y, T2.X, T3.X,
343 ; EG-NEXT:     AND_INT * T3.W, T3.X, literal.y,
344 ; EG-NEXT:    31(4.344025e-44), 32(4.484155e-44)
345 ; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, PV.Y,
346 ; EG-NEXT:     LSHR T4.Y, T0.Y, PV.X,
347 ; EG-NEXT:     CNDE_INT T1.Z, T1.W, T4.X, T4.Z,
348 ; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.Y, T0.X, T1.X, BS:VEC_102/SCL_221
349 ; EG-NEXT:     AND_INT * T4.W, T1.X, literal.x,
350 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
351 ; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, PV.Y,
352 ; EG-NEXT:     ADD_INT T0.W, KC0[2].Y, literal.x,
353 ; EG-NEXT:     CNDE_INT * T2.W, T0.Z, T1.Y, 0.0,
354 ; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
355 ; EG-NEXT:     LSHR T0.X, PV.W, literal.x,
356 ; EG-NEXT:     CNDE_INT T2.Y, T3.W, T3.Y, 0.0,
357 ; EG-NEXT:     CNDE_INT T1.W, T1.W, T4.Z, 0.0, BS:VEC_120/SCL_212
358 ; EG-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
359 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
360 ; EG-NEXT:     CNDE_INT * T1.Y, T4.W, T4.Y, 0.0,
395 ; EG-LABEL: s_lshr_32_i64:
396 ; EG:       ; %bb.0:
397 ; EG-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
398 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
399 ; EG-NEXT:    CF_END
400 ; EG-NEXT:    PAD
401 ; EG-NEXT:    ALU clause starting at 4:
402 ; EG-NEXT:     MOV T0.X, KC0[5].X,
403 ; EG-NEXT:     MOV T0.Y, 0.0,
404 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
405 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
448 ; EG-LABEL: v_lshr_32_i64:
449 ; EG:       ; %bb.0:
450 ; EG-NEXT:    ALU 2, @8, KC0[CB0:0-32], KC1[]
451 ; EG-NEXT:    TEX 0 @6
452 ; EG-NEXT:    ALU 3, @11, KC0[CB0:0-32], KC1[]
453 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
454 ; EG-NEXT:    CF_END
455 ; EG-NEXT:    PAD
456 ; EG-NEXT:    Fetch clause starting at 6:
457 ; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 4, #1
458 ; EG-NEXT:    ALU clause starting at 8:
459 ; EG-NEXT:     LSHL * T0.W, T0.X, literal.x,
460 ; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
461 ; EG-NEXT:     ADD_INT * T0.X, KC0[2].Z, PV.W,
462 ; EG-NEXT:    ALU clause starting at 11:
463 ; EG-NEXT:     MOV T0.Y, 0.0,
464 ; EG-NEXT:     ADD_INT * T0.W, KC0[2].Y, T0.W,
465 ; EG-NEXT:     LSHR * T1.X, PV.W, literal.x,
466 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)