Lines Matching refs:SI
2 …ch=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
12 ; SI-LABEL: sgpr_if_else_salu_br:
13 ; SI: ; %bb.0: ; %entry
14 ; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xb
15 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
16 ; SI-NEXT: s_load_dword s0, s[0:1], 0xf
17 ; SI-NEXT: s_waitcnt lgkmcnt(0)
18 ; SI-NEXT: s_cmp_lg_u32 s8, 0
19 ; SI-NEXT: s_cbranch_scc0 .LBB0_4
20 ; SI-NEXT: ; %bb.1: ; %else
21 ; SI-NEXT: s_add_i32 s2, s11, s0
22 ; SI-NEXT: s_cbranch_execnz .LBB0_3
23 ; SI-NEXT: .LBB0_2: ; %if
24 ; SI-NEXT: s_sub_i32 s2, s9, s10
25 ; SI-NEXT: .LBB0_3: ; %endif
26 ; SI-NEXT: s_add_i32 s0, s2, s8
27 ; SI-NEXT: s_mov_b32 s7, 0xf000
28 ; SI-NEXT: s_mov_b32 s6, -1
29 ; SI-NEXT: v_mov_b32_e32 v0, s0
30 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
31 ; SI-NEXT: s_endpgm
32 ; SI-NEXT: .LBB0_4:
33 ; SI-NEXT: ; implicit-def: $sgpr2
34 ; SI-NEXT: s_branch .LBB0_2
56 ; SI-LABEL: sgpr_if_else_salu_br_opt:
57 ; SI: ; %bb.0: ; %entry
58 ; SI-NEXT: s_load_dword s6, s[0:1], 0x13
59 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
60 ; SI-NEXT: s_waitcnt lgkmcnt(0)
61 ; SI-NEXT: s_cmp_lg_u32 s6, 0
62 ; SI-NEXT: s_cbranch_scc0 .LBB1_4
63 ; SI-NEXT: ; %bb.1: ; %else
64 ; SI-NEXT: s_load_dword s2, s[0:1], 0x2e
65 ; SI-NEXT: s_load_dword s3, s[0:1], 0x37
66 ; SI-NEXT: s_waitcnt lgkmcnt(0)
67 ; SI-NEXT: s_add_i32 s7, s2, s3
68 ; SI-NEXT: s_cbranch_execnz .LBB1_3
69 ; SI-NEXT: .LBB1_2: ; %if
70 ; SI-NEXT: s_load_dword s2, s[0:1], 0x1c
71 ; SI-NEXT: s_load_dword s0, s[0:1], 0x25
72 ; SI-NEXT: s_waitcnt lgkmcnt(0)
73 ; SI-NEXT: s_add_i32 s7, s2, s0
74 ; SI-NEXT: .LBB1_3: ; %endif
75 ; SI-NEXT: s_add_i32 s0, s7, s6
76 ; SI-NEXT: s_mov_b32 s7, 0xf000
77 ; SI-NEXT: s_mov_b32 s6, -1
78 ; SI-NEXT: v_mov_b32_e32 v0, s0
79 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
80 ; SI-NEXT: s_endpgm
81 ; SI-NEXT: .LBB1_4:
82 ; SI-NEXT: ; implicit-def: $sgpr7
83 ; SI-NEXT: s_branch .LBB1_2
107 ; SI-LABEL: sgpr_if_else_valu_br:
108 ; SI: ; %bb.0: ; %entry
109 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
110 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xc
111 ; SI-NEXT: v_cvt_f32_u32_e32 v0, v0
112 ; SI-NEXT: ; implicit-def: $sgpr8
113 ; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0
114 ; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc
115 ; SI-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
116 ; SI-NEXT: s_cbranch_execz .LBB2_2
117 ; SI-NEXT: ; %bb.1: ; %else
118 ; SI-NEXT: s_waitcnt lgkmcnt(0)
119 ; SI-NEXT: s_add_i32 s8, s2, s3
120 ; SI-NEXT: .LBB2_2: ; %Flow
121 ; SI-NEXT: s_waitcnt lgkmcnt(0)
122 ; SI-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
123 ; SI-NEXT: v_mov_b32_e32 v0, s8
124 ; SI-NEXT: s_xor_b64 exec, exec, s[2:3]
125 ; SI-NEXT: ; %bb.3: ; %if
126 ; SI-NEXT: s_add_i32 s0, s0, s1
127 ; SI-NEXT: v_mov_b32_e32 v0, s0
128 ; SI-NEXT: ; %bb.4: ; %endif
129 ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
130 ; SI-NEXT: s_mov_b32 s7, 0xf000
131 ; SI-NEXT: s_mov_b32 s6, -1
132 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
133 ; SI-NEXT: s_endpgm
155 ; SI-LABEL: sgpr_if_else_valu_cmp_phi_br:
156 ; SI: ; %bb.0: ; %entry
157 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
158 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
159 ; SI-NEXT: s_mov_b32 s2, 0
160 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
161 ; SI-NEXT: ; implicit-def: $sgpr8_sgpr9
162 ; SI-NEXT: s_and_saveexec_b64 s[10:11], vcc
163 ; SI-NEXT: s_xor_b64 s[10:11], exec, s[10:11]
164 ; SI-NEXT: s_cbranch_execz .LBB3_2
165 ; SI-NEXT: ; %bb.1: ; %else
166 ; SI-NEXT: s_mov_b32 s3, 0xf000
167 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
168 ; SI-NEXT: v_mov_b32_e32 v1, 0
169 ; SI-NEXT: s_waitcnt lgkmcnt(0)
170 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
171 ; SI-NEXT: s_waitcnt vmcnt(0)
172 ; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
173 ; SI-NEXT: s_and_b64 s[8:9], vcc, exec
174 ; SI-NEXT: ; implicit-def: $vgpr0
175 ; SI-NEXT: .LBB3_2: ; %Flow
176 ; SI-NEXT: s_waitcnt lgkmcnt(0)
177 ; SI-NEXT: s_andn2_saveexec_b64 s[0:1], s[10:11]
178 ; SI-NEXT: s_cbranch_execz .LBB3_4
179 ; SI-NEXT: ; %bb.3: ; %if
180 ; SI-NEXT: s_mov_b32 s15, 0xf000
181 ; SI-NEXT: s_mov_b32 s14, 0
182 ; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
183 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
184 ; SI-NEXT: v_mov_b32_e32 v1, 0
185 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
186 ; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], exec
187 ; SI-NEXT: s_waitcnt vmcnt(0)
188 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
189 ; SI-NEXT: s_and_b64 s[6:7], vcc, exec
190 ; SI-NEXT: s_or_b64 s[8:9], s[2:3], s[6:7]
191 ; SI-NEXT: .LBB3_4: ; %endif
192 ; SI-NEXT: s_or_b64 exec, exec, s[0:1]
193 ; SI-NEXT: s_mov_b32 s7, 0xf000
194 ; SI-NEXT: s_mov_b32 s6, -1
195 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[8:9]
196 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
197 ; SI-NEXT: s_endpgm