Lines Matching refs:T0

9 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
13 ; CM-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,
14 ; CM-NEXT:     AND_INT T0.Z, KC0[2].W, literal.y,
15 ; CM-NEXT:     AND_INT * T0.W, KC0[2].Z, literal.y,
17 ; CM-NEXT:     MULLO_INT T1.X, T0.W, T0.Z,
18 ; CM-NEXT:     MULLO_INT T1.Y (MASKED), T0.W, T0.Z,
19 ; CM-NEXT:     MULLO_INT T1.Z (MASKED), T0.W, T0.Z,
20 ; CM-NEXT:     MULLO_INT * T1.W (MASKED), T0.W, T0.Z,
25 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
29 ; EG-NEXT:     AND_INT T0.W, KC0[2].W, literal.x,
32 ; EG-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,
52 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
56 ; CM-NEXT:     VTX_READ_16 T1.X, T0.X, 40, #3
57 ; CM-NEXT:     VTX_READ_16 T0.X, T0.X, 42, #3
59 ; CM-NEXT:     MOV * T0.X, 0.0,
61 ; CM-NEXT:     MULLO_INT T0.X, T1.X, T0.X,
62 ; CM-NEXT:     MULLO_INT T0.Y (MASKED), T1.X, T0.X,
63 ; CM-NEXT:     MULLO_INT T0.Z (MASKED), T1.X, T0.X,
64 ; CM-NEXT:     MULLO_INT * T0.W (MASKED), T1.X, T0.X,
65 ; CM-NEXT:     BFE_INT * T0.X, PV.X, 0.0, literal.x,
75 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
79 ; EG-NEXT:     VTX_READ_16 T1.X, T0.X, 40, #3
80 ; EG-NEXT:     VTX_READ_16 T0.X, T0.X, 42, #3
82 ; EG-NEXT:     MOV * T0.X, 0.0,
84 ; EG-NEXT:     MULLO_INT * T0.X, T1.X, T0.X,
85 ; EG-NEXT:     BFE_INT T0.X, PS, 0.0, literal.x,
102 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
106 ; CM-NEXT:     VTX_READ_8 T1.X, T0.X, 40, #3
107 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 41, #3
109 ; CM-NEXT:     MOV * T0.X, 0.0,
111 ; CM-NEXT:     MULLO_INT T0.X, T1.X, T0.X,
112 ; CM-NEXT:     MULLO_INT T0.Y (MASKED), T1.X, T0.X,
113 ; CM-NEXT:     MULLO_INT T0.Z (MASKED), T1.X, T0.X,
114 ; CM-NEXT:     MULLO_INT * T0.W (MASKED), T1.X, T0.X,
115 ; CM-NEXT:     BFE_INT * T0.X, PV.X, 0.0, literal.x,
125 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
129 ; EG-NEXT:     VTX_READ_8 T1.X, T0.X, 40, #3
130 ; EG-NEXT:     VTX_READ_8 T0.X, T0.X, 41, #3
132 ; EG-NEXT:     MOV * T0.X, 0.0,
134 ; EG-NEXT:     MULLO_INT * T0.X, T1.X, T0.X,
135 ; EG-NEXT:     BFE_INT T0.X, PS, 0.0, literal.x,
149 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
153 ; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
163 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
167 ; EG-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
186 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
190 ; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
200 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
204 ; EG-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
222 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
226 ; CM-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,
227 ; CM-NEXT:     AND_INT * T0.Z, KC0[3].Y, literal.y,
229 ; CM-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
231 ; CM-NEXT:     MULLO_INT T1.X, T0.W, T0.Z,
232 ; CM-NEXT:     MULLO_INT T1.Y (MASKED), T0.W, T0.Z,
233 ; CM-NEXT:     MULLO_INT T1.Z (MASKED), T0.W, T0.Z,
234 ; CM-NEXT:     MULLO_INT * T1.W (MASKED), T0.W, T0.Z,
243 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
247 ; EG-NEXT:     AND_INT T0.W, KC0[3].Y, literal.x,
250 ; EG-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,