Lines Matching refs:CM

2 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefixes=CM %s
6 ; CM-LABEL: test_umul24_i32:
7 ; CM:       ; %bb.0: ; %entry
8 ; CM-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
9 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
10 ; CM-NEXT:    CF_END
11 ; CM-NEXT:    PAD
12 ; CM-NEXT:    ALU clause starting at 4:
13 ; CM-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,
14 ; CM-NEXT:     AND_INT T0.Z, KC0[2].W, literal.y,
15 ; CM-NEXT:     AND_INT * T0.W, KC0[2].Z, literal.y,
16 ; CM-NEXT:    2(2.802597e-45), 16777215(2.350989e-38)
17 ; CM-NEXT:     MULLO_INT T1.X, T0.W, T0.Z,
18 ; CM-NEXT:     MULLO_INT T1.Y (MASKED), T0.W, T0.Z,
19 ; CM-NEXT:     MULLO_INT T1.Z (MASKED), T0.W, T0.Z,
20 ; CM-NEXT:     MULLO_INT * T1.W (MASKED), T0.W, T0.Z,
47 ; CM-LABEL: test_umul24_i16_sext:
48 ; CM:       ; %bb.0: ; %entry
49 ; CM-NEXT:    ALU 0, @10, KC0[], KC1[]
50 ; CM-NEXT:    TEX 1 @6
51 ; CM-NEXT:    ALU 7, @11, KC0[CB0:0-32], KC1[]
52 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
53 ; CM-NEXT:    CF_END
54 ; CM-NEXT:    PAD
55 ; CM-NEXT:    Fetch clause starting at 6:
56 ; CM-NEXT:     VTX_READ_16 T1.X, T0.X, 40, #3
57 ; CM-NEXT:     VTX_READ_16 T0.X, T0.X, 42, #3
58 ; CM-NEXT:    ALU clause starting at 10:
59 ; CM-NEXT:     MOV * T0.X, 0.0,
60 ; CM-NEXT:    ALU clause starting at 11:
61 ; CM-NEXT:     MULLO_INT T0.X, T1.X, T0.X,
62 ; CM-NEXT:     MULLO_INT T0.Y (MASKED), T1.X, T0.X,
63 ; CM-NEXT:     MULLO_INT T0.Z (MASKED), T1.X, T0.X,
64 ; CM-NEXT:     MULLO_INT * T0.W (MASKED), T1.X, T0.X,
65 ; CM-NEXT:     BFE_INT * T0.X, PV.X, 0.0, literal.x,
66 ; CM-NEXT:    16(2.242078e-44), 0(0.000000e+00)
67 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
68 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
97 ; CM-LABEL: test_umul24_i8:
98 ; CM:       ; %bb.0: ; %entry
99 ; CM-NEXT:    ALU 0, @10, KC0[], KC1[]
100 ; CM-NEXT:    TEX 1 @6
101 ; CM-NEXT:    ALU 7, @11, KC0[CB0:0-32], KC1[]
102 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
103 ; CM-NEXT:    CF_END
104 ; CM-NEXT:    PAD
105 ; CM-NEXT:    Fetch clause starting at 6:
106 ; CM-NEXT:     VTX_READ_8 T1.X, T0.X, 40, #3
107 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 41, #3
108 ; CM-NEXT:    ALU clause starting at 10:
109 ; CM-NEXT:     MOV * T0.X, 0.0,
110 ; CM-NEXT:    ALU clause starting at 11:
111 ; CM-NEXT:     MULLO_INT T0.X, T1.X, T0.X,
112 ; CM-NEXT:     MULLO_INT T0.Y (MASKED), T1.X, T0.X,
113 ; CM-NEXT:     MULLO_INT T0.Z (MASKED), T1.X, T0.X,
114 ; CM-NEXT:     MULLO_INT * T0.W (MASKED), T1.X, T0.X,
115 ; CM-NEXT:     BFE_INT * T0.X, PV.X, 0.0, literal.x,
116 ; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
117 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
118 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
146 ; CM-LABEL: test_umulhi24_i32_i64:
147 ; CM:       ; %bb.0: ; %entry
148 ; CM-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
149 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
150 ; CM-NEXT:    CF_END
151 ; CM-NEXT:    PAD
152 ; CM-NEXT:    ALU clause starting at 4:
153 ; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
154 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
155 ; CM-NEXT:     MULHI_UINT24 T1.X, KC0[2].Z, KC0[2].W,
156 ; CM-NEXT:     MULHI_UINT24 T1.Y (MASKED), KC0[2].Z, KC0[2].W,
157 ; CM-NEXT:     MULHI_UINT24 T1.Z (MASKED), KC0[2].Z, KC0[2].W,
158 ; CM-NEXT:     MULHI_UINT24 * T1.W (MASKED), KC0[2].Z, KC0[2].W,
183 ; CM-LABEL: test_umulhi24:
184 ; CM:       ; %bb.0: ; %entry
185 ; CM-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
186 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
187 ; CM-NEXT:    CF_END
188 ; CM-NEXT:    PAD
189 ; CM-NEXT:    ALU clause starting at 4:
190 ; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
191 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
192 ; CM-NEXT:     MULHI_UINT24 T1.X, KC0[2].W, KC0[3].Y,
193 ; CM-NEXT:     MULHI_UINT24 T1.Y (MASKED), KC0[2].W, KC0[3].Y,
194 ; CM-NEXT:     MULHI_UINT24 T1.Z (MASKED), KC0[2].W, KC0[3].Y,
195 ; CM-NEXT:     MULHI_UINT24 * T1.W (MASKED), KC0[2].W, KC0[3].Y,
219 ; CM-LABEL: test_umul24_i64:
220 ; CM:       ; %bb.0: ; %entry
221 ; CM-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
222 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
223 ; CM-NEXT:    CF_END
224 ; CM-NEXT:    PAD
225 ; CM-NEXT:    ALU clause starting at 4:
226 ; CM-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,
227 ; CM-NEXT:     AND_INT * T0.Z, KC0[3].Y, literal.y,
228 ; CM-NEXT:    2(2.802597e-45), 16777215(2.350989e-38)
229 ; CM-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
230 ; CM-NEXT:    16777215(2.350989e-38), 0(0.000000e+00)
231 ; CM-NEXT:     MULLO_INT T1.X, T0.W, T0.Z,
232 ; CM-NEXT:     MULLO_INT T1.Y (MASKED), T0.W, T0.Z,
233 ; CM-NEXT:     MULLO_INT T1.Z (MASKED), T0.W, T0.Z,
234 ; CM-NEXT:     MULLO_INT * T1.W (MASKED), T0.W, T0.Z,
235 ; CM-NEXT:     MULHI_UINT24 T1.X (MASKED), KC0[2].W, KC0[3].Y,
236 ; CM-NEXT:     MULHI_UINT24 T1.Y, KC0[2].W, KC0[3].Y,
237 ; CM-NEXT:     MULHI_UINT24 T1.Z (MASKED), KC0[2].W, KC0[3].Y,
238 ; CM-NEXT:     MULHI_UINT24 * T1.W (MASKED), KC0[2].W, KC0[3].Y,