Lines Matching refs:CM
6 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
69 ; CM-LABEL: test_smul24_i32:
70 ; CM: ; %bb.0: ; %entry
71 ; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]
72 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
73 ; CM-NEXT: CF_END
74 ; CM-NEXT: PAD
75 ; CM-NEXT: ALU clause starting at 4:
76 ; CM-NEXT: LSHL T0.Z, KC0[2].Z, literal.x,
77 ; CM-NEXT: LSHL * T0.W, KC0[2].W, literal.x,
78 ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
79 ; CM-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
80 ; CM-NEXT: ASHR T1.Z, PV.W, literal.y,
81 ; CM-NEXT: ASHR * T0.W, PV.Z, literal.y,
82 ; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44)
83 ; CM-NEXT: MULLO_INT T1.X, T0.W, T1.Z,
84 ; CM-NEXT: MULLO_INT T1.Y (MASKED), T0.W, T1.Z,
85 ; CM-NEXT: MULLO_INT T1.Z (MASKED), T0.W, T1.Z,
86 ; CM-NEXT: MULLO_INT * T1.W (MASKED), T0.W, T1.Z,
153 ; CM-LABEL: test_smulhi24_i64:
154 ; CM: ; %bb.0: ; %entry
155 ; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
156 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
157 ; CM-NEXT: CF_END
158 ; CM-NEXT: PAD
159 ; CM-NEXT: ALU clause starting at 4:
160 ; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
161 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
162 ; CM-NEXT: MULHI_INT24 T1.X, KC0[2].Z, KC0[2].W,
163 ; CM-NEXT: MULHI_INT24 T1.Y (MASKED), KC0[2].Z, KC0[2].W,
164 ; CM-NEXT: MULHI_INT24 T1.Z (MASKED), KC0[2].Z, KC0[2].W,
165 ; CM-NEXT: MULHI_INT24 * T1.W (MASKED), KC0[2].Z, KC0[2].W,
210 ; CM-LABEL: test_smul48_i64:
211 ; CM: ; %bb.0:
212 ; CM-NEXT: CF_END
213 ; CM-NEXT: PAD
279 ; CM-LABEL: test_smul48_v2i64:
280 ; CM: ; %bb.0:
281 ; CM-NEXT: CF_END
282 ; CM-NEXT: PAD
364 ; CM-LABEL: test_smul24_i64:
365 ; CM: ; %bb.0:
366 ; CM-NEXT: ALU 14, @4, KC0[CB0:0-32], KC1[]
367 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
368 ; CM-NEXT: CF_END
369 ; CM-NEXT: PAD
370 ; CM-NEXT: ALU clause starting at 4:
371 ; CM-NEXT: LSHL T0.Z, KC0[4].Z, literal.x,
372 ; CM-NEXT: LSHL * T0.W, KC0[6].W, literal.x,
373 ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
374 ; CM-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
375 ; CM-NEXT: ASHR T1.Z, PV.W, literal.y,
376 ; CM-NEXT: ASHR * T0.W, PV.Z, literal.y,
377 ; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44)
378 ; CM-NEXT: MULLO_INT T1.X, T1.Z, T0.W,
379 ; CM-NEXT: MULLO_INT T1.Y (MASKED), T1.Z, T0.W,
380 ; CM-NEXT: MULLO_INT T1.Z (MASKED), T1.Z, T0.W,
381 ; CM-NEXT: MULLO_INT * T1.W (MASKED), T1.Z, T0.W,
382 ; CM-NEXT: MULHI_INT24 T1.X (MASKED), KC0[6].W, KC0[4].Z,
383 ; CM-NEXT: MULHI_INT24 T1.Y, KC0[6].W, KC0[4].Z,
384 ; CM-NEXT: MULHI_INT24 T1.Z (MASKED), KC0[6].W, KC0[4].Z,
385 ; CM-NEXT: MULHI_INT24 * T1.W (MASKED), KC0[6].W, KC0[4].Z,
456 ; CM-LABEL: test_smul24_i64_square:
457 ; CM: ; %bb.0:
458 ; CM-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
459 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
460 ; CM-NEXT: CF_END
461 ; CM-NEXT: PAD
462 ; CM-NEXT: ALU clause starting at 4:
463 ; CM-NEXT: LSHL * T0.W, KC0[2].Z, literal.x,
464 ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
465 ; CM-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
466 ; CM-NEXT: ASHR * T0.W, PV.W, literal.y,
467 ; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44)
468 ; CM-NEXT: MULLO_INT T1.X, T0.W, T0.W,
469 ; CM-NEXT: MULLO_INT T1.Y (MASKED), T0.W, T0.W,
470 ; CM-NEXT: MULLO_INT T1.Z (MASKED), T0.W, T0.W,
471 ; CM-NEXT: MULLO_INT * T1.W (MASKED), T0.W, T0.W,
472 ; CM-NEXT: MULHI_INT24 T1.X (MASKED), KC0[2].Z, KC0[2].Z,
473 ; CM-NEXT: MULHI_INT24 T1.Y, KC0[2].Z, KC0[2].Z,
474 ; CM-NEXT: MULHI_INT24 T1.Z (MASKED), KC0[2].Z, KC0[2].Z,
475 ; CM-NEXT: MULHI_INT24 * T1.W (MASKED), KC0[2].Z, KC0[2].Z,
566 ; CM-LABEL: test_smul24_i33:
567 ; CM: ; %bb.0: ; %entry
568 ; CM-NEXT: ALU 16, @4, KC0[CB0:0-32], KC1[]
569 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T2.X
570 ; CM-NEXT: CF_END
571 ; CM-NEXT: PAD
572 ; CM-NEXT: ALU clause starting at 4:
573 ; CM-NEXT: LSHL T0.Z, KC0[2].W, literal.x,
574 ; CM-NEXT: LSHL * T0.W, KC0[3].Y, literal.x,
575 ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
576 ; CM-NEXT: ASHR T1.Z, PV.W, literal.x,
577 ; CM-NEXT: ASHR * T0.W, PV.Z, literal.x,
578 ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
579 ; CM-NEXT: MULHI_INT24 T0.X, KC0[2].W, KC0[3].Y,
580 ; CM-NEXT: MULHI_INT24 T0.Y (MASKED), KC0[2].W, KC0[3].Y,
581 ; CM-NEXT: MULHI_INT24 T0.Z (MASKED), KC0[2].W, KC0[3].Y,
582 ; CM-NEXT: MULHI_INT24 * T0.W (MASKED), KC0[2].W, KC0[3].Y,
583 ; CM-NEXT: MULLO_INT T1.X, T0.W, T1.Z,
584 ; CM-NEXT: MULLO_INT T1.Y (MASKED), T0.W, T1.Z,
585 ; CM-NEXT: MULLO_INT T1.Z (MASKED), T0.W, T1.Z,
586 ; CM-NEXT: MULLO_INT * T1.W (MASKED), T0.W, T1.Z,
587 ; CM-NEXT: LSHR T2.X, KC0[2].Y, literal.x,
588 ; CM-NEXT: BFE_INT * T1.Y, T0.X, 0.0, 1,
589 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
666 ; CM-LABEL: test_smulhi24_i33:
667 ; CM: ; %bb.0: ; %entry
668 ; CM-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]
669 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
670 ; CM-NEXT: CF_END
671 ; CM-NEXT: PAD
672 ; CM-NEXT: ALU clause starting at 4:
673 ; CM-NEXT: MULHI_INT24 T0.X, KC0[2].W, KC0[3].Y,
674 ; CM-NEXT: MULHI_INT24 T0.Y (MASKED), KC0[2].W, KC0[3].Y,
675 ; CM-NEXT: MULHI_INT24 T0.Z (MASKED), KC0[2].W, KC0[3].Y,
676 ; CM-NEXT: MULHI_INT24 * T0.W (MASKED), KC0[2].W, KC0[3].Y,
677 ; CM-NEXT: AND_INT * T0.X, PV.X, 1,
678 ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
679 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
784 ; CM-LABEL: simplify_i24_crash:
785 ; CM: ; %bb.0: ; %bb
786 ; CM-NEXT: ALU_PUSH_BEFORE 1, @6, KC0[CB0:0-32], KC1[]
787 ; CM-NEXT: JUMP @5 POP:1
788 ; CM-NEXT: ALU 13, @8, KC0[CB0:0-32], KC1[]
789 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
790 ; CM-NEXT: POP @5 POP:1
791 ; CM-NEXT: CF_END
792 ; CM-NEXT: ALU clause starting at 6:
793 ; CM-NEXT: SETNE_INT * T0.W, KC0[2].Z, 0.0,
794 ; CM-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,
795 ; CM-NEXT: ALU clause starting at 8:
796 ; CM-NEXT: LSHL T0.Z, KC0[2].W, literal.x,
797 ; CM-NEXT: LSHL * T0.W, KC0[3].Y, literal.x,
798 ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
799 ; CM-NEXT: MOV T0.Y, KC0[2].Y,
800 ; CM-NEXT: ASHR T1.Z, PV.W, literal.x,
801 ; CM-NEXT: ASHR * T0.W, PV.Z, literal.x,
802 ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
803 ; CM-NEXT: MULLO_INT T0.X, T0.W, T1.Z,
804 ; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Z,
805 ; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Z,
806 ; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T1.Z,
807 ; CM-NEXT: LSHR T1.X, T0.Y, literal.x,
808 ; CM-NEXT: MOV * T0.Y, PV.X,
809 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)