Lines Matching refs:Lower

32 ; GCN-O0-NEXT:    Lower ctors and dtors for AMDGPU
35 ; GCN-O0-NEXT:    AMDGPU Lower Intrinsics
41 ; GCN-O0-NEXT:    Lower OpenCL enqueued blocks
42 ; GCN-O0-NEXT:    Lower uses of LDS variables from non-kernel functions
45 ; GCN-O0-NEXT:      Lower constant intrinsics
55 ; GCN-O0-NEXT:        AMDGPU Lower Kernel Arguments
57 ; GCN-O0-NEXT:        Lower SwitchInst's to branches
58 ; GCN-O0-NEXT:        Lower invoke and unwind, for unwindless code generators
66 ; GCN-O0-NEXT:        Lower SwitchInst's to branches
98 ; GCN-O0-NEXT:        SI Lower i1 Copies
103 ; GCN-O0-NEXT:        SI Lower control flow pseudo instructions
167 ; GCN-O1-NEXT:    Lower ctors and dtors for AMDGPU
170 ; GCN-O1-NEXT:    AMDGPU Lower Intrinsics
176 ; GCN-O1-NEXT:    Lower OpenCL enqueued blocks
177 ; GCN-O1-NEXT:    Lower uses of LDS variables from non-kernel functions
202 ; GCN-O1-NEXT:      Lower constant intrinsics
221 ; GCN-O1-NEXT:        AMDGPU Lower Kernel Arguments
226 ; GCN-O1-NEXT:        Lower SwitchInst's to branches
227 ; GCN-O1-NEXT:        Lower invoke and unwind, for unwindless code generators
244 ; GCN-O1-NEXT:        Lower SwitchInst's to branches
281 ; GCN-O1-NEXT:        SI Lower i1 Copies
316 ; GCN-O1-NEXT:        SI Lower control flow pseudo instructions
424 ; GCN-O1-OPTS-NEXT:    Lower ctors and dtors for AMDGPU
427 ; GCN-O1-OPTS-NEXT:    AMDGPU Lower Intrinsics
433 ; GCN-O1-OPTS-NEXT:    Lower OpenCL enqueued blocks
434 ; GCN-O1-OPTS-NEXT:    Lower uses of LDS variables from non-kernel functions
477 ; GCN-O1-OPTS-NEXT:      Lower constant intrinsics
497 ; GCN-O1-OPTS-NEXT:        AMDGPU Lower Kernel Arguments
508 ; GCN-O1-OPTS-NEXT:        Lower SwitchInst's to branches
509 ; GCN-O1-OPTS-NEXT:        Lower invoke and unwind, for unwindless code generators
526 ; GCN-O1-OPTS-NEXT:        Lower SwitchInst's to branches
563 ; GCN-O1-OPTS-NEXT:        SI Lower i1 Copies
605 ; GCN-O1-OPTS-NEXT:        SI Lower control flow pseudo instructions
714 ; GCN-O2-NEXT:    Lower ctors and dtors for AMDGPU
717 ; GCN-O2-NEXT:    AMDGPU Lower Intrinsics
723 ; GCN-O2-NEXT:    Lower OpenCL enqueued blocks
724 ; GCN-O2-NEXT:    Lower uses of LDS variables from non-kernel functions
767 ; GCN-O2-NEXT:      Lower constant intrinsics
787 ; GCN-O2-NEXT:        AMDGPU Lower Kernel Arguments
798 ; GCN-O2-NEXT:        Lower SwitchInst's to branches
799 ; GCN-O2-NEXT:        Lower invoke and unwind, for unwindless code generators
816 ; GCN-O2-NEXT:        Lower SwitchInst's to branches
854 ; GCN-O2-NEXT:        SI Lower i1 Copies
896 ; GCN-O2-NEXT:        SI Lower control flow pseudo instructions
1007 ; GCN-O3-NEXT:    Lower ctors and dtors for AMDGPU
1010 ; GCN-O3-NEXT:    AMDGPU Lower Intrinsics
1016 ; GCN-O3-NEXT:    Lower OpenCL enqueued blocks
1017 ; GCN-O3-NEXT:    Lower uses of LDS variables from non-kernel functions
1065 ; GCN-O3-NEXT:      Lower constant intrinsics
1092 ; GCN-O3-NEXT:        AMDGPU Lower Kernel Arguments
1103 ; GCN-O3-NEXT:        Lower SwitchInst's to branches
1104 ; GCN-O3-NEXT:        Lower invoke and unwind, for unwindless code generators
1121 ; GCN-O3-NEXT:        Lower SwitchInst's to branches
1159 ; GCN-O3-NEXT:        SI Lower i1 Copies
1201 ; GCN-O3-NEXT:        SI Lower control flow pseudo instructions