Lines Matching refs:CM

6 ; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -check-prefixes=EGCM,CM …
60 ; CM-LABEL: i8_arg:
61 ; CM:       ; %bb.0:
62 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
63 ; CM-NEXT:    TEX 0 @6
64 ; CM-NEXT:    ALU 1, @9, KC0[CB0:0-32], KC1[]
65 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
66 ; CM-NEXT:    CF_END
67 ; CM-NEXT:    PAD
68 ; CM-NEXT:    Fetch clause starting at 6:
69 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 40, #3
70 ; CM-NEXT:    ALU clause starting at 8:
71 ; CM-NEXT:     MOV * T0.X, 0.0,
72 ; CM-NEXT:    ALU clause starting at 9:
73 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
74 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
133 ; CM-LABEL: i8_zext_arg:
134 ; CM:       ; %bb.0:
135 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
136 ; CM-NEXT:    TEX 0 @6
137 ; CM-NEXT:    ALU 3, @9, KC0[CB0:0-32], KC1[]
138 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
139 ; CM-NEXT:    CF_END
140 ; CM-NEXT:    PAD
141 ; CM-NEXT:    Fetch clause starting at 6:
142 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 40, #3
143 ; CM-NEXT:    ALU clause starting at 8:
144 ; CM-NEXT:     MOV * T0.X, 0.0,
145 ; CM-NEXT:    ALU clause starting at 9:
146 ; CM-NEXT:     BFE_INT * T0.X, T0.X, 0.0, literal.x,
147 ; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
148 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
149 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
208 ; CM-LABEL: i8_sext_arg:
209 ; CM:       ; %bb.0:
210 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
211 ; CM-NEXT:    TEX 0 @6
212 ; CM-NEXT:    ALU 3, @9, KC0[CB0:0-32], KC1[]
213 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
214 ; CM-NEXT:    CF_END
215 ; CM-NEXT:    PAD
216 ; CM-NEXT:    Fetch clause starting at 6:
217 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 40, #3
218 ; CM-NEXT:    ALU clause starting at 8:
219 ; CM-NEXT:     MOV * T0.X, 0.0,
220 ; CM-NEXT:    ALU clause starting at 9:
221 ; CM-NEXT:     BFE_INT * T0.X, T0.X, 0.0, literal.x,
222 ; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
223 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
224 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
282 ; CM-LABEL: i16_arg:
283 ; CM:       ; %bb.0:
284 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
285 ; CM-NEXT:    TEX 0 @6
286 ; CM-NEXT:    ALU 1, @9, KC0[CB0:0-32], KC1[]
287 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
288 ; CM-NEXT:    CF_END
289 ; CM-NEXT:    PAD
290 ; CM-NEXT:    Fetch clause starting at 6:
291 ; CM-NEXT:     VTX_READ_16 T0.X, T0.X, 40, #3
292 ; CM-NEXT:    ALU clause starting at 8:
293 ; CM-NEXT:     MOV * T0.X, 0.0,
294 ; CM-NEXT:    ALU clause starting at 9:
295 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
296 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
355 ; CM-LABEL: i16_zext_arg:
356 ; CM:       ; %bb.0:
357 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
358 ; CM-NEXT:    TEX 0 @6
359 ; CM-NEXT:    ALU 3, @9, KC0[CB0:0-32], KC1[]
360 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
361 ; CM-NEXT:    CF_END
362 ; CM-NEXT:    PAD
363 ; CM-NEXT:    Fetch clause starting at 6:
364 ; CM-NEXT:     VTX_READ_16 T0.X, T0.X, 40, #3
365 ; CM-NEXT:    ALU clause starting at 8:
366 ; CM-NEXT:     MOV * T0.X, 0.0,
367 ; CM-NEXT:    ALU clause starting at 9:
368 ; CM-NEXT:     BFE_INT * T0.X, T0.X, 0.0, literal.x,
369 ; CM-NEXT:    16(2.242078e-44), 0(0.000000e+00)
370 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
371 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
430 ; CM-LABEL: i16_sext_arg:
431 ; CM:       ; %bb.0:
432 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
433 ; CM-NEXT:    TEX 0 @6
434 ; CM-NEXT:    ALU 3, @9, KC0[CB0:0-32], KC1[]
435 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
436 ; CM-NEXT:    CF_END
437 ; CM-NEXT:    PAD
438 ; CM-NEXT:    Fetch clause starting at 6:
439 ; CM-NEXT:     VTX_READ_16 T0.X, T0.X, 40, #3
440 ; CM-NEXT:    ALU clause starting at 8:
441 ; CM-NEXT:     MOV * T0.X, 0.0,
442 ; CM-NEXT:    ALU clause starting at 9:
443 ; CM-NEXT:     BFE_INT * T0.X, T0.X, 0.0, literal.x,
444 ; CM-NEXT:    16(2.242078e-44), 0(0.000000e+00)
445 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
446 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
496 ; CM-LABEL: i32_arg:
497 ; CM:       ; %bb.0: ; %entry
498 ; CM-NEXT:    ALU 2, @4, KC0[CB0:0-32], KC1[]
499 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
500 ; CM-NEXT:    CF_END
501 ; CM-NEXT:    PAD
502 ; CM-NEXT:    ALU clause starting at 4:
503 ; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
504 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
505 ; CM-NEXT:     MOV * T1.X, KC0[2].Z,
555 ; CM-LABEL: f32_arg:
556 ; CM:       ; %bb.0: ; %entry
557 ; CM-NEXT:    ALU 2, @4, KC0[CB0:0-32], KC1[]
558 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
559 ; CM-NEXT:    CF_END
560 ; CM-NEXT:    PAD
561 ; CM-NEXT:    ALU clause starting at 4:
562 ; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
563 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
564 ; CM-NEXT:     MOV * T1.X, KC0[2].Z,
634 ; CM-LABEL: v2i8_arg:
635 ; CM:       ; %bb.0: ; %entry
636 ; CM-NEXT:    ALU 0, @10, KC0[], KC1[]
637 ; CM-NEXT:    TEX 1 @6
638 ; CM-NEXT:    ALU 15, @11, KC0[CB0:0-32], KC1[]
639 ; CM-NEXT:    MEM_RAT MSKOR T4.XW, T5.X
640 ; CM-NEXT:    CF_END
641 ; CM-NEXT:    PAD
642 ; CM-NEXT:    Fetch clause starting at 6:
643 ; CM-NEXT:     VTX_READ_8 T5.X, T4.X, 41, #3
644 ; CM-NEXT:     VTX_READ_8 T4.X, T4.X, 40, #3
645 ; CM-NEXT:    ALU clause starting at 10:
646 ; CM-NEXT:     MOV * T4.X, 0.0,
647 ; CM-NEXT:    ALU clause starting at 11:
648 ; CM-NEXT:     LSHL T0.Z, T5.X, literal.x,
649 ; CM-NEXT:     AND_INT * T0.W, T4.X, literal.y, BS:VEC_120/SCL_212
650 ; CM-NEXT:    8(1.121039e-44), 255(3.573311e-43)
651 ; CM-NEXT:     AND_INT T1.Z, KC0[2].Y, literal.x,
652 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
653 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
654 ; CM-NEXT:     AND_INT T0.Z, PV.W, literal.x,
655 ; CM-NEXT:     LSHL * T0.W, PV.Z, literal.y,
656 ; CM-NEXT:    65535(9.183409e-41), 3(4.203895e-45)
657 ; CM-NEXT:     LSHL T4.X, PV.Z, PV.W,
658 ; CM-NEXT:     LSHL * T4.W, literal.x, PV.W,
659 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
660 ; CM-NEXT:     MOV T4.Y, 0.0,
661 ; CM-NEXT:     MOV * T4.Z, 0.0,
662 ; CM-NEXT:     LSHR * T5.X, KC0[2].Y, literal.x,
663 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
723 ; CM-LABEL: v2i16_arg:
724 ; CM:       ; %bb.0: ; %entry
725 ; CM-NEXT:    ALU 0, @10, KC0[], KC1[]
726 ; CM-NEXT:    TEX 1 @6
727 ; CM-NEXT:    ALU 5, @11, KC0[CB0:0-32], KC1[]
728 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T4.X, T5.X
729 ; CM-NEXT:    CF_END
730 ; CM-NEXT:    PAD
731 ; CM-NEXT:    Fetch clause starting at 6:
732 ; CM-NEXT:     VTX_READ_16 T5.X, T4.X, 42, #3
733 ; CM-NEXT:     VTX_READ_16 T4.X, T4.X, 40, #3
734 ; CM-NEXT:    ALU clause starting at 10:
735 ; CM-NEXT:     MOV * T4.X, 0.0,
736 ; CM-NEXT:    ALU clause starting at 11:
737 ; CM-NEXT:     LSHL T0.Z, T5.X, literal.x,
738 ; CM-NEXT:     AND_INT * T0.W, T4.X, literal.y, BS:VEC_120/SCL_212
739 ; CM-NEXT:    16(2.242078e-44), 65535(9.183409e-41)
740 ; CM-NEXT:     OR_INT * T4.X, PV.Z, PV.W,
741 ; CM-NEXT:     LSHR * T5.X, KC0[2].Y, literal.x,
742 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
796 ; CM-LABEL: v2i32_arg:
797 ; CM:       ; %bb.0: ; %entry
798 ; CM-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
799 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
800 ; CM-NEXT:    CF_END
801 ; CM-NEXT:    PAD
802 ; CM-NEXT:    ALU clause starting at 4:
803 ; CM-NEXT:     MOV * T0.Y, KC0[3].X,
804 ; CM-NEXT:     MOV * T0.X, KC0[2].W,
805 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
806 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
860 ; CM-LABEL: v2f32_arg:
861 ; CM:       ; %bb.0: ; %entry
862 ; CM-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
863 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
864 ; CM-NEXT:    CF_END
865 ; CM-NEXT:    PAD
866 ; CM-NEXT:    ALU clause starting at 4:
867 ; CM-NEXT:     MOV * T0.Y, KC0[3].X,
868 ; CM-NEXT:     MOV * T0.X, KC0[2].W,
869 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
870 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
965 ; CM-LABEL: v3i8_arg:
966 ; CM:       ; %bb.0: ; %entry
967 ; CM-NEXT:    ALU 0, @12, KC0[], KC1[]
968 ; CM-NEXT:    TEX 2 @6
969 ; CM-NEXT:    ALU 29, @13, KC0[CB0:0-32], KC1[]
970 ; CM-NEXT:    MEM_RAT MSKOR T4.XW, T7.X
971 ; CM-NEXT:    MEM_RAT MSKOR T5.XW, T6.X
972 ; CM-NEXT:    CF_END
973 ; CM-NEXT:    Fetch clause starting at 6:
974 ; CM-NEXT:     VTX_READ_8 T5.X, T4.X, 41, #3
975 ; CM-NEXT:     VTX_READ_8 T6.X, T4.X, 42, #3
976 ; CM-NEXT:     VTX_READ_8 T4.X, T4.X, 40, #3
977 ; CM-NEXT:    ALU clause starting at 12:
978 ; CM-NEXT:     MOV * T4.X, 0.0,
979 ; CM-NEXT:    ALU clause starting at 13:
980 ; CM-NEXT:     LSHL T0.Z, T5.X, literal.x,
981 ; CM-NEXT:     AND_INT * T0.W, T4.X, literal.y, BS:VEC_120/SCL_212
982 ; CM-NEXT:    8(1.121039e-44), 255(3.573311e-43)
983 ; CM-NEXT:     AND_INT T1.Z, KC0[2].Y, literal.x,
984 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
985 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
986 ; CM-NEXT:     AND_INT T0.Z, PV.W, literal.x,
987 ; CM-NEXT:     LSHL * T0.W, PV.Z, literal.y,
988 ; CM-NEXT:    65535(9.183409e-41), 3(4.203895e-45)
989 ; CM-NEXT:     LSHL T4.X, PV.Z, PV.W,
990 ; CM-NEXT:     LSHL * T4.W, literal.x, PV.W,
991 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
992 ; CM-NEXT:     MOV T4.Y, 0.0,
993 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
994 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
995 ; CM-NEXT:     AND_INT * T1.W, PV.W, literal.x,
996 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
997 ; CM-NEXT:     AND_INT T0.Z, T6.X, literal.x,
998 ; CM-NEXT:     LSHL * T1.W, PV.W, literal.y,
999 ; CM-NEXT:    255(3.573311e-43), 3(4.203895e-45)
1000 ; CM-NEXT:     LSHL T5.X, PV.Z, PV.W,
1001 ; CM-NEXT:     LSHL * T5.W, literal.x, PV.W,
1002 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
1003 ; CM-NEXT:     MOV T5.Y, 0.0,
1004 ; CM-NEXT:     MOV * T4.Z, 0.0,
1005 ; CM-NEXT:     MOV * T5.Z, 0.0,
1006 ; CM-NEXT:     LSHR * T6.X, T0.W, literal.x,
1007 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1008 ; CM-NEXT:     LSHR * T7.X, KC0[2].Y, literal.x,
1009 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1095 ; CM-LABEL: v3i16_arg:
1096 ; CM:       ; %bb.0: ; %entry
1097 ; CM-NEXT:    ALU 0, @12, KC0[], KC1[]
1098 ; CM-NEXT:    TEX 2 @6
1099 ; CM-NEXT:    ALU 19, @13, KC0[CB0:0-32], KC1[]
1100 ; CM-NEXT:    MEM_RAT MSKOR T5.XW, T8.X
1101 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T6.X, T7.X
1102 ; CM-NEXT:    CF_END
1103 ; CM-NEXT:    Fetch clause starting at 6:
1104 ; CM-NEXT:     VTX_READ_16 T6.X, T5.X, 44, #3
1105 ; CM-NEXT:     VTX_READ_16 T7.X, T5.X, 46, #3
1106 ; CM-NEXT:     VTX_READ_16 T5.X, T5.X, 48, #3
1107 ; CM-NEXT:    ALU clause starting at 12:
1108 ; CM-NEXT:     MOV * T5.X, 0.0,
1109 ; CM-NEXT:    ALU clause starting at 13:
1110 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
1111 ; CM-NEXT:    4(5.605194e-45), 0(0.000000e+00)
1112 ; CM-NEXT:     AND_INT * T1.W, PV.W, literal.x,
1113 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
1114 ; CM-NEXT:     AND_INT T0.Z, T5.X, literal.x,
1115 ; CM-NEXT:     LSHL * T1.W, PV.W, literal.y,
1116 ; CM-NEXT:    65535(9.183409e-41), 3(4.203895e-45)
1117 ; CM-NEXT:     LSHL T5.X, PV.Z, PV.W,
1118 ; CM-NEXT:     LSHL * T5.W, literal.x, PV.W,
1119 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
1120 ; CM-NEXT:     MOV T5.Y, 0.0,
1121 ; CM-NEXT:     MOV * T5.Z, 0.0,
1122 ; CM-NEXT:     LSHL T0.Z, T7.X, literal.x,
1123 ; CM-NEXT:     AND_INT * T1.W, T6.X, literal.y, BS:VEC_120/SCL_212
1124 ; CM-NEXT:    16(2.242078e-44), 65535(9.183409e-41)
1125 ; CM-NEXT:     OR_INT * T6.X, PV.Z, PV.W,
1126 ; CM-NEXT:     LSHR * T7.X, KC0[2].Y, literal.x,
1127 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1128 ; CM-NEXT:     LSHR * T8.X, T0.W, literal.x,
1129 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1193 ; CM-LABEL: v3i32_arg:
1194 ; CM:       ; %bb.0: ; %entry
1195 ; CM-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
1196 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T3.X
1197 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
1198 ; CM-NEXT:    CF_END
1199 ; CM-NEXT:    ALU clause starting at 4:
1200 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
1201 ; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
1202 ; CM-NEXT:     LSHR * T0.X, PV.W, literal.x,
1203 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1204 ; CM-NEXT:     MOV T1.X, KC0[3].W,
1205 ; CM-NEXT:     MOV * T2.Y, KC0[3].Z,
1206 ; CM-NEXT:     MOV * T2.X, KC0[3].Y,
1207 ; CM-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
1208 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1272 ; CM-LABEL: v3f32_arg:
1273 ; CM:       ; %bb.0: ; %entry
1274 ; CM-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
1275 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T3.X
1276 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
1277 ; CM-NEXT:    CF_END
1278 ; CM-NEXT:    ALU clause starting at 4:
1279 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
1280 ; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
1281 ; CM-NEXT:     LSHR * T0.X, PV.W, literal.x,
1282 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1283 ; CM-NEXT:     MOV T1.X, KC0[3].W,
1284 ; CM-NEXT:     MOV * T2.Y, KC0[3].Z,
1285 ; CM-NEXT:     MOV * T2.X, KC0[3].Y,
1286 ; CM-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
1287 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1359 ; CM-LABEL: v4i8_arg:
1360 ; CM:       ; %bb.0: ; %entry
1361 ; CM-NEXT:    ALU 0, @14, KC0[], KC1[]
1362 ; CM-NEXT:    TEX 3 @6
1363 ; CM-NEXT:    ALU 15, @15, KC0[CB0:0-32], KC1[]
1364 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T4.X, T5.X
1365 ; CM-NEXT:    CF_END
1366 ; CM-NEXT:    PAD
1367 ; CM-NEXT:    Fetch clause starting at 6:
1368 ; CM-NEXT:     VTX_READ_8 T5.X, T4.X, 42, #3
1369 ; CM-NEXT:     VTX_READ_8 T6.X, T4.X, 40, #3
1370 ; CM-NEXT:     VTX_READ_8 T7.X, T4.X, 43, #3
1371 ; CM-NEXT:     VTX_READ_8 T4.X, T4.X, 41, #3
1372 ; CM-NEXT:    ALU clause starting at 14:
1373 ; CM-NEXT:     MOV * T4.X, 0.0,
1374 ; CM-NEXT:    ALU clause starting at 15:
1375 ; CM-NEXT:     AND_INT * T0.W, T5.X, literal.x,
1376 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
1377 ; CM-NEXT:     AND_INT T0.Y, T4.X, literal.x,
1378 ; CM-NEXT:     LSHL T0.Z, PV.W, literal.y,
1379 ; CM-NEXT:     LSHL * T0.W, T7.X, literal.z, BS:VEC_120/SCL_212
1380 ; CM-NEXT:    255(3.573311e-43), 16(2.242078e-44)
1381 ; CM-NEXT:    24(3.363116e-44), 0(0.000000e+00)
1382 ; CM-NEXT:     OR_INT T0.Z, PV.W, PV.Z,
1383 ; CM-NEXT:     LSHL * T0.W, PV.Y, literal.x,
1384 ; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
1385 ; CM-NEXT:     OR_INT T0.Z, PV.Z, PV.W,
1386 ; CM-NEXT:     AND_INT * T0.W, T6.X, literal.x,
1387 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
1388 ; CM-NEXT:     OR_INT * T4.X, PV.Z, PV.W,
1389 ; CM-NEXT:     LSHR * T5.X, KC0[2].Y, literal.x,
1390 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1488 ; CM-LABEL: v4i16_arg:
1489 ; CM:       ; %bb.0: ; %entry
1490 ; CM-NEXT:    ALU 1, @20, KC0[], KC1[]
1491 ; CM-NEXT:    TEX 0 @12
1492 ; CM-NEXT:    ALU 5, @22, KC0[], KC1[]
1493 ; CM-NEXT:    TEX 0 @14
1494 ; CM-NEXT:    ALU 5, @28, KC0[], KC1[]
1495 ; CM-NEXT:    TEX 0 @16
1496 ; CM-NEXT:    ALU 5, @34, KC0[], KC1[]
1497 ; CM-NEXT:    TEX 0 @18
1498 ; CM-NEXT:    ALU 7, @40, KC0[CB0:0-32], KC1[]
1499 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T5, T6.X
1500 ; CM-NEXT:    CF_END
1501 ; CM-NEXT:    PAD
1502 ; CM-NEXT:    Fetch clause starting at 12:
1503 ; CM-NEXT:     VTX_READ_16 T6.X, T5.X, 50, #3
1504 ; CM-NEXT:    Fetch clause starting at 14:
1505 ; CM-NEXT:     VTX_READ_16 T6.X, T5.X, 48, #3
1506 ; CM-NEXT:    Fetch clause starting at 16:
1507 ; CM-NEXT:     VTX_READ_16 T6.X, T5.X, 46, #3
1508 ; CM-NEXT:    Fetch clause starting at 18:
1509 ; CM-NEXT:     VTX_READ_16 T5.X, T5.X, 44, #3
1510 ; CM-NEXT:    ALU clause starting at 20:
1511 ; CM-NEXT:     MOV * T0.Y, T3.X,
1512 ; CM-NEXT:     MOV * T5.X, 0.0,
1513 ; CM-NEXT:    ALU clause starting at 22:
1514 ; CM-NEXT:     LSHL T0.Z, T6.X, literal.x,
1515 ; CM-NEXT:     AND_INT * T0.W, T0.Y, literal.y,
1516 ; CM-NEXT:    16(2.242078e-44), 65535(9.183409e-41)
1517 ; CM-NEXT:     OR_INT * T0.W, PV.W, PV.Z,
1518 ; CM-NEXT:     MOV * T3.X, PV.W,
1519 ; CM-NEXT:     MOV * T0.Y, PV.X,
1520 ; CM-NEXT:    ALU clause starting at 28:
1521 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
1522 ; CM-NEXT:     AND_INT * T0.W, T6.X, literal.y,
1523 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
1524 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
1525 ; CM-NEXT:     MOV T3.X, PV.W,
1526 ; CM-NEXT:     MOV * T0.Y, T2.X,
1527 ; CM-NEXT:    ALU clause starting at 34:
1528 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
1529 ; CM-NEXT:     LSHL * T0.W, T6.X, literal.y,
1530 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
1531 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
1532 ; CM-NEXT:     MOV * T2.X, PV.W,
1533 ; CM-NEXT:     MOV * T0.Y, PV.X,
1534 ; CM-NEXT:    ALU clause starting at 40:
1535 ; CM-NEXT:     LSHR T6.X, KC0[2].Y, literal.x,
1536 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.y,
1537 ; CM-NEXT:     AND_INT * T0.W, T5.X, literal.z,
1538 ; CM-NEXT:    2(2.802597e-45), -65536(nan)
1539 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
1540 ; CM-NEXT:     OR_INT * T5.X, PV.Z, PV.W,
1541 ; CM-NEXT:     MOV T2.X, PV.X,
1542 ; CM-NEXT:     MOV * T5.Y, T3.X,
1604 ; CM-LABEL: v4i32_arg:
1605 ; CM:       ; %bb.0: ; %entry
1606 ; CM-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
1607 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
1608 ; CM-NEXT:    CF_END
1609 ; CM-NEXT:    PAD
1610 ; CM-NEXT:    ALU clause starting at 4:
1611 ; CM-NEXT:     MOV * T0.W, KC0[4].X,
1612 ; CM-NEXT:     MOV * T0.Z, KC0[3].W,
1613 ; CM-NEXT:     MOV * T0.Y, KC0[3].Z,
1614 ; CM-NEXT:     MOV * T0.X, KC0[3].Y,
1615 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
1616 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1678 ; CM-LABEL: v4f32_arg:
1679 ; CM:       ; %bb.0: ; %entry
1680 ; CM-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
1681 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
1682 ; CM-NEXT:    CF_END
1683 ; CM-NEXT:    PAD
1684 ; CM-NEXT:    ALU clause starting at 4:
1685 ; CM-NEXT:     MOV * T0.W, KC0[4].X,
1686 ; CM-NEXT:     MOV * T0.Z, KC0[3].W,
1687 ; CM-NEXT:     MOV * T0.Y, KC0[3].Z,
1688 ; CM-NEXT:     MOV * T0.X, KC0[3].Y,
1689 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
1690 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1789 ; CM-LABEL: v5i8_arg:
1790 ; CM:       ; %bb.0: ; %entry
1791 ; CM-NEXT:    ALU 0, @16, KC0[], KC1[]
1792 ; CM-NEXT:    TEX 4 @6
1793 ; CM-NEXT:    ALU 28, @17, KC0[CB0:0-32], KC1[]
1794 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T6.X, T8.X
1795 ; CM-NEXT:    MEM_RAT MSKOR T5.XW, T7.X
1796 ; CM-NEXT:    CF_END
1797 ; CM-NEXT:    Fetch clause starting at 6:
1798 ; CM-NEXT:     VTX_READ_8 T6.X, T5.X, 44, #3
1799 ; CM-NEXT:     VTX_READ_8 T7.X, T5.X, 47, #3
1800 ; CM-NEXT:     VTX_READ_8 T8.X, T5.X, 45, #3
1801 ; CM-NEXT:     VTX_READ_8 T9.X, T5.X, 46, #3
1802 ; CM-NEXT:     VTX_READ_8 T5.X, T5.X, 48, #3
1803 ; CM-NEXT:    ALU clause starting at 16:
1804 ; CM-NEXT:     MOV * T5.X, 0.0,
1805 ; CM-NEXT:    ALU clause starting at 17:
1806 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
1807 ; CM-NEXT:    4(5.605194e-45), 0(0.000000e+00)
1808 ; CM-NEXT:     AND_INT * T1.W, PV.W, literal.x,
1809 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
1810 ; CM-NEXT:     AND_INT T0.Z, T5.X, literal.x,
1811 ; CM-NEXT:     LSHL * T1.W, PV.W, literal.y,
1812 ; CM-NEXT:    255(3.573311e-43), 3(4.203895e-45)
1813 ; CM-NEXT:     LSHL T5.X, PV.Z, PV.W,
1814 ; CM-NEXT:     LSHL * T5.W, literal.x, PV.W,
1815 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
1816 ; CM-NEXT:     MOV T5.Y, 0.0,
1817 ; CM-NEXT:     MOV T5.Z, 0.0,
1818 ; CM-NEXT:     AND_INT * T1.W, T9.X, literal.x,
1819 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
1820 ; CM-NEXT:     AND_INT T0.Y, T8.X, literal.x,
1821 ; CM-NEXT:     LSHL T0.Z, PV.W, literal.y,
1822 ; CM-NEXT:     LSHL * T1.W, T7.X, literal.z, BS:VEC_120/SCL_212
1823 ; CM-NEXT:    255(3.573311e-43), 16(2.242078e-44)
1824 ; CM-NEXT:    24(3.363116e-44), 0(0.000000e+00)
1825 ; CM-NEXT:     OR_INT T0.Z, PV.W, PV.Z,
1826 ; CM-NEXT:     LSHL * T1.W, PV.Y, literal.x,
1827 ; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
1828 ; CM-NEXT:     LSHR T7.X, T0.W, literal.x,
1829 ; CM-NEXT:     OR_INT T0.Z, PV.Z, PV.W,
1830 ; CM-NEXT:     AND_INT * T0.W, T6.X, literal.y,
1831 ; CM-NEXT:    2(2.802597e-45), 255(3.573311e-43)
1832 ; CM-NEXT:     OR_INT * T6.X, PV.Z, PV.W,
1833 ; CM-NEXT:     LSHR * T8.X, KC0[2].Y, literal.x,
1834 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1977 ; CM-LABEL: v5i16_arg:
1978 ; CM:       ; %bb.0: ; %entry
1979 ; CM-NEXT:    ALU 0, @20, KC0[], KC1[]
1980 ; CM-NEXT:    TEX 4 @10
1981 ; CM-NEXT:    ALU 67, @21, KC0[CB0:0-32], KC1[]
1982 ; CM-NEXT:    MEM_RAT MSKOR T5.XW, T9.X
1983 ; CM-NEXT:    MEM_RAT MSKOR T4.XW, T7.X
1984 ; CM-NEXT:    MEM_RAT MSKOR T3.XW, T2.X
1985 ; CM-NEXT:    MEM_RAT MSKOR T6.XW, T1.X
1986 ; CM-NEXT:    MEM_RAT MSKOR T8.XW, T0.X
1987 ; CM-NEXT:    CF_END
1988 ; CM-NEXT:    PAD
1989 ; CM-NEXT:    Fetch clause starting at 10:
1990 ; CM-NEXT:     VTX_READ_16 T1.X, T0.X, 58, #3
1991 ; CM-NEXT:     VTX_READ_16 T2.X, T0.X, 56, #3
1992 ; CM-NEXT:     VTX_READ_16 T3.X, T0.X, 54, #3
1993 ; CM-NEXT:     VTX_READ_16 T4.X, T0.X, 52, #3
1994 ; CM-NEXT:     VTX_READ_16 T0.X, T0.X, 60, #3
1995 ; CM-NEXT:    ALU clause starting at 20:
1996 ; CM-NEXT:     MOV * T0.X, 0.0,
1997 ; CM-NEXT:    ALU clause starting at 21:
1998 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
1999 ; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
2000 ; CM-NEXT:     AND_INT * T1.W, PV.W, literal.x,
2001 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
2002 ; CM-NEXT:     AND_INT T0.Z, T0.X, literal.x,
2003 ; CM-NEXT:     LSHL * T1.W, PV.W, literal.y,
2004 ; CM-NEXT:    65535(9.183409e-41), 3(4.203895e-45)
2005 ; CM-NEXT:     LSHL T5.X, PV.Z, PV.W,
2006 ; CM-NEXT:     LSHL * T5.W, literal.x, PV.W,
2007 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
2008 ; CM-NEXT:     MOV T5.Y, 0.0,
2009 ; CM-NEXT:     AND_INT * T1.W, KC0[2].Y, literal.x,
2010 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
2011 ; CM-NEXT:     AND_INT T0.Z, T4.X, literal.x,
2012 ; CM-NEXT:     LSHL * T1.W, PV.W, literal.y,
2013 ; CM-NEXT:    65535(9.183409e-41), 3(4.203895e-45)
2014 ; CM-NEXT:     LSHL T4.X, PV.Z, PV.W,
2015 ; CM-NEXT:     LSHL * T4.W, literal.x, PV.W,
2016 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
2017 ; CM-NEXT:     MOV T4.Y, 0.0,
2018 ; CM-NEXT:     ADD_INT * T1.W, KC0[2].Y, literal.x,
2019 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2020 ; CM-NEXT:     AND_INT * T2.W, PV.W, literal.x,
2021 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
2022 ; CM-NEXT:     AND_INT T0.Z, T3.X, literal.x,
2023 ; CM-NEXT:     LSHL * T2.W, PV.W, literal.y,
2024 ; CM-NEXT:    65535(9.183409e-41), 3(4.203895e-45)
2025 ; CM-NEXT:     LSHL T3.X, PV.Z, PV.W,
2026 ; CM-NEXT:     LSHL * T3.W, literal.x, PV.W,
2027 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
2028 ; CM-NEXT:     MOV T3.Y, 0.0,
2029 ; CM-NEXT:     ADD_INT * T2.W, KC0[2].Y, literal.x,
2030 ; CM-NEXT:    4(5.605194e-45), 0(0.000000e+00)
2031 ; CM-NEXT:     AND_INT * T6.W, PV.W, literal.x,
2032 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
2033 ; CM-NEXT:     AND_INT T0.Z, T2.X, literal.x,
2034 ; CM-NEXT:     LSHL * T6.W, PV.W, literal.y,
2035 ; CM-NEXT:    65535(9.183409e-41), 3(4.203895e-45)
2036 ; CM-NEXT:     LSHL T6.X, PV.Z, PV.W,
2037 ; CM-NEXT:     LSHL * T6.W, literal.x, PV.W,
2038 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
2039 ; CM-NEXT:     MOV T6.Y, 0.0,
2040 ; CM-NEXT:     ADD_INT * T7.W, KC0[2].Y, literal.x,
2041 ; CM-NEXT:    6(8.407791e-45), 0(0.000000e+00)
2042 ; CM-NEXT:     AND_INT * T8.W, PV.W, literal.x,
2043 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
2044 ; CM-NEXT:     AND_INT T0.Z, T1.X, literal.x,
2045 ; CM-NEXT:     LSHL * T8.W, PV.W, literal.y,
2046 ; CM-NEXT:    65535(9.183409e-41), 3(4.203895e-45)
2047 ; CM-NEXT:     LSHL T8.X, PV.Z, PV.W,
2048 ; CM-NEXT:     LSHL * T8.W, literal.x, PV.W,
2049 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
2050 ; CM-NEXT:     MOV T8.Y, 0.0,
2051 ; CM-NEXT:     MOV * T5.Z, 0.0,
2052 ; CM-NEXT:     MOV * T4.Z, 0.0,
2053 ; CM-NEXT:     MOV * T3.Z, 0.0,
2054 ; CM-NEXT:     MOV * T6.Z, 0.0,
2055 ; CM-NEXT:     MOV * T8.Z, 0.0,
2056 ; CM-NEXT:     LSHR * T0.X, T7.W, literal.x,
2057 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2058 ; CM-NEXT:     LSHR * T1.X, T2.W, literal.x,
2059 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2060 ; CM-NEXT:     LSHR * T2.X, T1.W, literal.x,
2061 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2062 ; CM-NEXT:     LSHR * T7.X, KC0[2].Y, literal.x,
2063 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2064 ; CM-NEXT:     LSHR * T9.X, T0.W, literal.x,
2065 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2146 ; CM-LABEL: v5i32_arg:
2147 ; CM:       ; %bb.0: ; %entry
2148 ; CM-NEXT:    ALU 10, @4, KC0[CB0:0-32], KC1[]
2149 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
2150 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X
2151 ; CM-NEXT:    CF_END
2152 ; CM-NEXT:    ALU clause starting at 4:
2153 ; CM-NEXT:     ADD_INT T0.Z, KC0[2].Y, literal.x,
2154 ; CM-NEXT:     MOV * T0.W, KC0[5].X,
2155 ; CM-NEXT:    16(2.242078e-44), 0(0.000000e+00)
2156 ; CM-NEXT:     LSHR T1.X, PV.Z, literal.x,
2157 ; CM-NEXT:     MOV * T0.Z, KC0[4].W,
2158 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2159 ; CM-NEXT:     MOV T2.X, KC0[5].Y,
2160 ; CM-NEXT:     MOV * T0.Y, KC0[4].Z,
2161 ; CM-NEXT:     MOV * T0.X, KC0[4].Y,
2162 ; CM-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
2163 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2245 ; CM-LABEL: v5f32_arg:
2246 ; CM:       ; %bb.0: ; %entry
2247 ; CM-NEXT:    ALU 10, @4, KC0[CB0:0-32], KC1[]
2248 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
2249 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X
2250 ; CM-NEXT:    CF_END
2251 ; CM-NEXT:    ALU clause starting at 4:
2252 ; CM-NEXT:     ADD_INT T0.Z, KC0[2].Y, literal.x,
2253 ; CM-NEXT:     MOV * T0.W, KC0[5].X,
2254 ; CM-NEXT:    16(2.242078e-44), 0(0.000000e+00)
2255 ; CM-NEXT:     LSHR T1.X, PV.Z, literal.x,
2256 ; CM-NEXT:     MOV * T0.Z, KC0[4].W,
2257 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2258 ; CM-NEXT:     MOV T2.X, KC0[5].Y,
2259 ; CM-NEXT:     MOV * T0.Y, KC0[4].Z,
2260 ; CM-NEXT:     MOV * T0.X, KC0[4].Y,
2261 ; CM-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
2262 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2378 ; CM-LABEL: v5i64_arg:
2379 ; CM:       ; %bb.0: ; %entry
2380 ; CM-NEXT:    ALU 18, @6, KC0[CB0:0-32], KC1[]
2381 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T5.X
2382 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T4.X
2383 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T3.X
2384 ; CM-NEXT:    CF_END
2385 ; CM-NEXT:    PAD
2386 ; CM-NEXT:    ALU clause starting at 6:
2387 ; CM-NEXT:     MOV * T0.W, KC0[8].X,
2388 ; CM-NEXT:     MOV T1.Y, KC0[8].Z,
2389 ; CM-NEXT:     MOV * T0.Z, KC0[7].W,
2390 ; CM-NEXT:     MOV T1.X, KC0[8].Y,
2391 ; CM-NEXT:     MOV * T0.Y, KC0[7].Z,
2392 ; CM-NEXT:     MOV T0.X, KC0[7].Y,
2393 ; CM-NEXT:     ADD_INT T1.Z, KC0[2].Y, literal.x,
2394 ; CM-NEXT:     MOV * T2.W, KC0[7].X,
2395 ; CM-NEXT:    32(4.484155e-44), 0(0.000000e+00)
2396 ; CM-NEXT:     LSHR T3.X, PV.Z, literal.x,
2397 ; CM-NEXT:     MOV T2.Z, KC0[6].W,
2398 ; CM-NEXT:     ADD_INT * T1.W, KC0[2].Y, literal.y,
2399 ; CM-NEXT:    2(2.802597e-45), 16(2.242078e-44)
2400 ; CM-NEXT:     LSHR T4.X, PV.W, literal.x,
2401 ; CM-NEXT:     MOV * T2.Y, KC0[6].Z,
2402 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2403 ; CM-NEXT:     MOV * T2.X, KC0[6].Y,
2404 ; CM-NEXT:     LSHR * T5.X, KC0[2].Y, literal.x,
2405 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2521 ; CM-LABEL: v5f64_arg:
2522 ; CM:       ; %bb.0: ; %entry
2523 ; CM-NEXT:    ALU 18, @6, KC0[CB0:0-32], KC1[]
2524 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T5.X
2525 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T4.X
2526 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T3.X
2527 ; CM-NEXT:    CF_END
2528 ; CM-NEXT:    PAD
2529 ; CM-NEXT:    ALU clause starting at 6:
2530 ; CM-NEXT:     MOV * T0.W, KC0[8].X,
2531 ; CM-NEXT:     MOV T1.Y, KC0[8].Z,
2532 ; CM-NEXT:     MOV * T0.Z, KC0[7].W,
2533 ; CM-NEXT:     MOV T1.X, KC0[8].Y,
2534 ; CM-NEXT:     MOV * T0.Y, KC0[7].Z,
2535 ; CM-NEXT:     MOV T0.X, KC0[7].Y,
2536 ; CM-NEXT:     ADD_INT T1.Z, KC0[2].Y, literal.x,
2537 ; CM-NEXT:     MOV * T2.W, KC0[7].X,
2538 ; CM-NEXT:    32(4.484155e-44), 0(0.000000e+00)
2539 ; CM-NEXT:     LSHR T3.X, PV.Z, literal.x,
2540 ; CM-NEXT:     MOV T2.Z, KC0[6].W,
2541 ; CM-NEXT:     ADD_INT * T1.W, KC0[2].Y, literal.y,
2542 ; CM-NEXT:    2(2.802597e-45), 16(2.242078e-44)
2543 ; CM-NEXT:     LSHR T4.X, PV.W, literal.x,
2544 ; CM-NEXT:     MOV * T2.Y, KC0[6].Z,
2545 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2546 ; CM-NEXT:     MOV * T2.X, KC0[6].Y,
2547 ; CM-NEXT:     LSHR * T5.X, KC0[2].Y, literal.x,
2548 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2697 ; CM-LABEL: v8i8_arg:
2698 ; CM:       ; %bb.0: ; %entry
2699 ; CM-NEXT:    ALU 1, @36, KC0[], KC1[]
2700 ; CM-NEXT:    TEX 0 @20
2701 ; CM-NEXT:    ALU 5, @38, KC0[], KC1[]
2702 ; CM-NEXT:    TEX 0 @22
2703 ; CM-NEXT:    ALU 5, @44, KC0[], KC1[]
2704 ; CM-NEXT:    TEX 0 @24
2705 ; CM-NEXT:    ALU 7, @50, KC0[], KC1[]
2706 ; CM-NEXT:    TEX 0 @26
2707 ; CM-NEXT:    ALU 7, @58, KC0[], KC1[]
2708 ; CM-NEXT:    TEX 0 @28
2709 ; CM-NEXT:    ALU 7, @66, KC0[], KC1[]
2710 ; CM-NEXT:    TEX 0 @30
2711 ; CM-NEXT:    ALU 7, @74, KC0[], KC1[]
2712 ; CM-NEXT:    TEX 0 @32
2713 ; CM-NEXT:    ALU 5, @82, KC0[], KC1[]
2714 ; CM-NEXT:    TEX 0 @34
2715 ; CM-NEXT:    ALU 5, @88, KC0[CB0:0-32], KC1[]
2716 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T5, T6.X
2717 ; CM-NEXT:    CF_END
2718 ; CM-NEXT:    PAD
2719 ; CM-NEXT:    Fetch clause starting at 20:
2720 ; CM-NEXT:     VTX_READ_8 T6.X, T5.X, 51, #3
2721 ; CM-NEXT:    Fetch clause starting at 22:
2722 ; CM-NEXT:     VTX_READ_8 T6.X, T5.X, 47, #3
2723 ; CM-NEXT:    Fetch clause starting at 24:
2724 ; CM-NEXT:     VTX_READ_8 T6.X, T5.X, 50, #3
2725 ; CM-NEXT:    Fetch clause starting at 26:
2726 ; CM-NEXT:     VTX_READ_8 T6.X, T5.X, 46, #3
2727 ; CM-NEXT:    Fetch clause starting at 28:
2728 ; CM-NEXT:     VTX_READ_8 T6.X, T5.X, 49, #3
2729 ; CM-NEXT:    Fetch clause starting at 30:
2730 ; CM-NEXT:     VTX_READ_8 T6.X, T5.X, 45, #3
2731 ; CM-NEXT:    Fetch clause starting at 32:
2732 ; CM-NEXT:     VTX_READ_8 T6.X, T5.X, 48, #3
2733 ; CM-NEXT:    Fetch clause starting at 34:
2734 ; CM-NEXT:     VTX_READ_8 T5.X, T5.X, 44, #3
2735 ; CM-NEXT:    ALU clause starting at 36:
2736 ; CM-NEXT:     MOV * T0.Y, T2.X,
2737 ; CM-NEXT:     MOV * T5.X, 0.0,
2738 ; CM-NEXT:    ALU clause starting at 38:
2739 ; CM-NEXT:     LSHL T0.Z, T6.X, literal.x,
2740 ; CM-NEXT:     AND_INT * T0.W, T0.Y, literal.y,
2741 ; CM-NEXT:    24(3.363116e-44), 16777215(2.350989e-38)
2742 ; CM-NEXT:     OR_INT * T0.W, PV.W, PV.Z,
2743 ; CM-NEXT:     MOV T2.X, PV.W,
2744 ; CM-NEXT:     MOV * T0.Y, T3.X,
2745 ; CM-NEXT:    ALU clause starting at 44:
2746 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
2747 ; CM-NEXT:     LSHL * T0.W, T6.X, literal.y,
2748 ; CM-NEXT:    16777215(2.350989e-38), 24(3.363116e-44)
2749 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
2750 ; CM-NEXT:     MOV T3.X, PV.W,
2751 ; CM-NEXT:     MOV * T0.Y, T2.X,
2752 ; CM-NEXT:    ALU clause starting at 50:
2753 ; CM-NEXT:     AND_INT * T0.W, T6.X, literal.x,
2754 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
2755 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
2756 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
2757 ; CM-NEXT:    -16711681(-1.714704e+38), 16(2.242078e-44)
2758 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
2759 ; CM-NEXT:     MOV T2.X, PV.W,
2760 ; CM-NEXT:     MOV * T0.Y, T3.X,
2761 ; CM-NEXT:    ALU clause starting at 58:
2762 ; CM-NEXT:     AND_INT * T0.W, T6.X, literal.x,
2763 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
2764 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
2765 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
2766 ; CM-NEXT:    -16711681(-1.714704e+38), 16(2.242078e-44)
2767 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
2768 ; CM-NEXT:     MOV T3.X, PV.W,
2769 ; CM-NEXT:     MOV * T0.Y, T2.X,
2770 ; CM-NEXT:    ALU clause starting at 66:
2771 ; CM-NEXT:     AND_INT * T0.W, T6.X, literal.x,
2772 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
2773 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
2774 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
2775 ; CM-NEXT:    -65281(nan), 8(1.121039e-44)
2776 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
2777 ; CM-NEXT:     MOV T2.X, PV.W,
2778 ; CM-NEXT:     MOV * T0.Y, T3.X,
2779 ; CM-NEXT:    ALU clause starting at 74:
2780 ; CM-NEXT:     AND_INT * T0.W, T6.X, literal.x,
2781 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
2782 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
2783 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
2784 ; CM-NEXT:    -65281(nan), 8(1.121039e-44)
2785 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
2786 ; CM-NEXT:     MOV T3.X, PV.W,
2787 ; CM-NEXT:     MOV * T0.Y, T2.X,
2788 ; CM-NEXT:    ALU clause starting at 82:
2789 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
2790 ; CM-NEXT:     AND_INT * T0.W, T6.X, literal.y,
2791 ; CM-NEXT:    -256(nan), 255(3.573311e-43)
2792 ; CM-NEXT:     OR_INT * T5.Y, PV.Z, PV.W,
2793 ; CM-NEXT:     MOV T2.X, PV.Y,
2794 ; CM-NEXT:     MOV * T0.Y, T3.X,
2795 ; CM-NEXT:    ALU clause starting at 88:
2796 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
2797 ; CM-NEXT:     AND_INT * T0.W, T5.X, literal.y,
2798 ; CM-NEXT:    -256(nan), 255(3.573311e-43)
2799 ; CM-NEXT:     OR_INT * T5.X, PV.Z, PV.W,
2800 ; CM-NEXT:     LSHR * T6.X, KC0[2].Y, literal.x,
2801 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
2950 ; CM-LABEL: v8i16_arg:
2951 ; CM:       ; %bb.0: ; %entry
2952 ; CM-NEXT:    ALU 1, @36, KC0[], KC1[]
2953 ; CM-NEXT:    TEX 0 @20
2954 ; CM-NEXT:    ALU 5, @38, KC0[], KC1[]
2955 ; CM-NEXT:    TEX 0 @22
2956 ; CM-NEXT:    ALU 5, @44, KC0[], KC1[]
2957 ; CM-NEXT:    TEX 0 @24
2958 ; CM-NEXT:    ALU 5, @50, KC0[], KC1[]
2959 ; CM-NEXT:    TEX 0 @26
2960 ; CM-NEXT:    ALU 5, @56, KC0[], KC1[]
2961 ; CM-NEXT:    TEX 0 @28
2962 ; CM-NEXT:    ALU 5, @62, KC0[], KC1[]
2963 ; CM-NEXT:    TEX 0 @30
2964 ; CM-NEXT:    ALU 5, @68, KC0[], KC1[]
2965 ; CM-NEXT:    TEX 0 @32
2966 ; CM-NEXT:    ALU 5, @74, KC0[], KC1[]
2967 ; CM-NEXT:    TEX 0 @34
2968 ; CM-NEXT:    ALU 8, @80, KC0[CB0:0-32], KC1[]
2969 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T7, T8.X
2970 ; CM-NEXT:    CF_END
2971 ; CM-NEXT:    PAD
2972 ; CM-NEXT:    Fetch clause starting at 20:
2973 ; CM-NEXT:     VTX_READ_16 T8.X, T7.X, 66, #3
2974 ; CM-NEXT:    Fetch clause starting at 22:
2975 ; CM-NEXT:     VTX_READ_16 T8.X, T7.X, 58, #3
2976 ; CM-NEXT:    Fetch clause starting at 24:
2977 ; CM-NEXT:     VTX_READ_16 T8.X, T7.X, 64, #3
2978 ; CM-NEXT:    Fetch clause starting at 26:
2979 ; CM-NEXT:     VTX_READ_16 T8.X, T7.X, 56, #3
2980 ; CM-NEXT:    Fetch clause starting at 28:
2981 ; CM-NEXT:     VTX_READ_16 T8.X, T7.X, 62, #3
2982 ; CM-NEXT:    Fetch clause starting at 30:
2983 ; CM-NEXT:     VTX_READ_16 T8.X, T7.X, 54, #3
2984 ; CM-NEXT:    Fetch clause starting at 32:
2985 ; CM-NEXT:     VTX_READ_16 T8.X, T7.X, 60, #3
2986 ; CM-NEXT:    Fetch clause starting at 34:
2987 ; CM-NEXT:     VTX_READ_16 T7.X, T7.X, 52, #3
2988 ; CM-NEXT:    ALU clause starting at 36:
2989 ; CM-NEXT:     MOV * T0.Y, T3.X,
2990 ; CM-NEXT:     MOV * T7.X, 0.0,
2991 ; CM-NEXT:    ALU clause starting at 38:
2992 ; CM-NEXT:     LSHL T0.Z, T8.X, literal.x,
2993 ; CM-NEXT:     AND_INT * T0.W, T0.Y, literal.y,
2994 ; CM-NEXT:    16(2.242078e-44), 65535(9.183409e-41)
2995 ; CM-NEXT:     OR_INT * T0.W, PV.W, PV.Z,
2996 ; CM-NEXT:     MOV T3.X, PV.W,
2997 ; CM-NEXT:     MOV * T0.Y, T5.X,
2998 ; CM-NEXT:    ALU clause starting at 44:
2999 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3000 ; CM-NEXT:     LSHL * T0.W, T8.X, literal.y,
3001 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
3002 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3003 ; CM-NEXT:     MOV T5.X, PV.W,
3004 ; CM-NEXT:     MOV * T0.Y, T3.X,
3005 ; CM-NEXT:    ALU clause starting at 50:
3006 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3007 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.y,
3008 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
3009 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3010 ; CM-NEXT:     MOV T3.X, PV.W,
3011 ; CM-NEXT:     MOV * T0.Y, T5.X,
3012 ; CM-NEXT:    ALU clause starting at 56:
3013 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3014 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.y,
3015 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
3016 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3017 ; CM-NEXT:     MOV T5.X, PV.W,
3018 ; CM-NEXT:     MOV * T0.Y, T2.X,
3019 ; CM-NEXT:    ALU clause starting at 62:
3020 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3021 ; CM-NEXT:     LSHL * T0.W, T8.X, literal.y,
3022 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
3023 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3024 ; CM-NEXT:     MOV T2.X, PV.W,
3025 ; CM-NEXT:     MOV * T0.Y, T4.X,
3026 ; CM-NEXT:    ALU clause starting at 68:
3027 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3028 ; CM-NEXT:     LSHL * T0.W, T8.X, literal.y,
3029 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
3030 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3031 ; CM-NEXT:     MOV T4.X, PV.W,
3032 ; CM-NEXT:     MOV * T0.Y, T2.X,
3033 ; CM-NEXT:    ALU clause starting at 74:
3034 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3035 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.y,
3036 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
3037 ; CM-NEXT:     OR_INT * T7.Z, PV.Z, PV.W,
3038 ; CM-NEXT:     MOV T2.X, PV.Z,
3039 ; CM-NEXT:     MOV * T0.Y, T4.X,
3040 ; CM-NEXT:    ALU clause starting at 80:
3041 ; CM-NEXT:     LSHR T8.X, KC0[2].Y, literal.x,
3042 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.y,
3043 ; CM-NEXT:     AND_INT * T0.W, T7.X, literal.z,
3044 ; CM-NEXT:    2(2.802597e-45), -65536(nan)
3045 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
3046 ; CM-NEXT:     OR_INT * T7.X, PV.Z, PV.W,
3047 ; CM-NEXT:     MOV T4.X, PV.X,
3048 ; CM-NEXT:     MOV * T7.W, T3.X,
3049 ; CM-NEXT:     MOV * T7.Y, T5.X,
3140 ; CM-LABEL: v8i32_arg:
3141 ; CM:       ; %bb.0: ; %entry
3142 ; CM-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
3143 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T3.X
3144 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T2.X
3145 ; CM-NEXT:    CF_END
3146 ; CM-NEXT:    ALU clause starting at 4:
3147 ; CM-NEXT:     MOV * T0.W, KC0[6].X,
3148 ; CM-NEXT:     MOV * T0.Z, KC0[5].W,
3149 ; CM-NEXT:     MOV * T0.Y, KC0[5].Z,
3150 ; CM-NEXT:     MOV T0.X, KC0[5].Y,
3151 ; CM-NEXT:     MOV * T1.W, KC0[5].X,
3152 ; CM-NEXT:     MOV T1.Z, KC0[4].W,
3153 ; CM-NEXT:     ADD_INT * T2.W, KC0[2].Y, literal.x,
3154 ; CM-NEXT:    16(2.242078e-44), 0(0.000000e+00)
3155 ; CM-NEXT:     LSHR T2.X, PV.W, literal.x,
3156 ; CM-NEXT:     MOV * T1.Y, KC0[4].Z,
3157 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
3158 ; CM-NEXT:     MOV * T1.X, KC0[4].Y,
3159 ; CM-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
3160 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
3251 ; CM-LABEL: v8f32_arg:
3252 ; CM:       ; %bb.0: ; %entry
3253 ; CM-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
3254 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T3.X
3255 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T2.X
3256 ; CM-NEXT:    CF_END
3257 ; CM-NEXT:    ALU clause starting at 4:
3258 ; CM-NEXT:     MOV * T0.W, KC0[6].X,
3259 ; CM-NEXT:     MOV * T0.Z, KC0[5].W,
3260 ; CM-NEXT:     MOV * T0.Y, KC0[5].Z,
3261 ; CM-NEXT:     MOV T0.X, KC0[5].Y,
3262 ; CM-NEXT:     MOV * T1.W, KC0[5].X,
3263 ; CM-NEXT:     MOV T1.Z, KC0[4].W,
3264 ; CM-NEXT:     ADD_INT * T2.W, KC0[2].Y, literal.x,
3265 ; CM-NEXT:    16(2.242078e-44), 0(0.000000e+00)
3266 ; CM-NEXT:     LSHR T2.X, PV.W, literal.x,
3267 ; CM-NEXT:     MOV * T1.Y, KC0[4].Z,
3268 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
3269 ; CM-NEXT:     MOV * T1.X, KC0[4].Y,
3270 ; CM-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
3271 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
3522 ; CM-LABEL: v16i8_arg:
3523 ; CM:       ; %bb.0: ; %entry
3524 ; CM-NEXT:    ALU 1, @68, KC0[], KC1[]
3525 ; CM-NEXT:    TEX 0 @36
3526 ; CM-NEXT:    ALU 5, @70, KC0[], KC1[]
3527 ; CM-NEXT:    TEX 0 @38
3528 ; CM-NEXT:    ALU 5, @76, KC0[], KC1[]
3529 ; CM-NEXT:    TEX 0 @40
3530 ; CM-NEXT:    ALU 5, @82, KC0[], KC1[]
3531 ; CM-NEXT:    TEX 0 @42
3532 ; CM-NEXT:    ALU 5, @88, KC0[], KC1[]
3533 ; CM-NEXT:    TEX 0 @44
3534 ; CM-NEXT:    ALU 7, @94, KC0[], KC1[]
3535 ; CM-NEXT:    TEX 0 @46
3536 ; CM-NEXT:    ALU 7, @102, KC0[], KC1[]
3537 ; CM-NEXT:    TEX 0 @48
3538 ; CM-NEXT:    ALU 7, @110, KC0[], KC1[]
3539 ; CM-NEXT:    TEX 0 @50
3540 ; CM-NEXT:    ALU 7, @118, KC0[], KC1[]
3541 ; CM-NEXT:    TEX 0 @52
3542 ; CM-NEXT:    ALU 7, @126, KC0[], KC1[]
3543 ; CM-NEXT:    TEX 0 @54
3544 ; CM-NEXT:    ALU 7, @134, KC0[], KC1[]
3545 ; CM-NEXT:    TEX 0 @56
3546 ; CM-NEXT:    ALU 7, @142, KC0[], KC1[]
3547 ; CM-NEXT:    TEX 0 @58
3548 ; CM-NEXT:    ALU 7, @150, KC0[], KC1[]
3549 ; CM-NEXT:    TEX 0 @60
3550 ; CM-NEXT:    ALU 5, @158, KC0[], KC1[]
3551 ; CM-NEXT:    TEX 0 @62
3552 ; CM-NEXT:    ALU 5, @164, KC0[], KC1[]
3553 ; CM-NEXT:    TEX 0 @64
3554 ; CM-NEXT:    ALU 5, @170, KC0[], KC1[]
3555 ; CM-NEXT:    TEX 0 @66
3556 ; CM-NEXT:    ALU 5, @176, KC0[CB0:0-32], KC1[]
3557 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T7, T8.X
3558 ; CM-NEXT:    CF_END
3559 ; CM-NEXT:    PAD
3560 ; CM-NEXT:    Fetch clause starting at 36:
3561 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 67, #3
3562 ; CM-NEXT:    Fetch clause starting at 38:
3563 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 63, #3
3564 ; CM-NEXT:    Fetch clause starting at 40:
3565 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 59, #3
3566 ; CM-NEXT:    Fetch clause starting at 42:
3567 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 55, #3
3568 ; CM-NEXT:    Fetch clause starting at 44:
3569 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 66, #3
3570 ; CM-NEXT:    Fetch clause starting at 46:
3571 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 62, #3
3572 ; CM-NEXT:    Fetch clause starting at 48:
3573 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 58, #3
3574 ; CM-NEXT:    Fetch clause starting at 50:
3575 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 54, #3
3576 ; CM-NEXT:    Fetch clause starting at 52:
3577 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 65, #3
3578 ; CM-NEXT:    Fetch clause starting at 54:
3579 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 61, #3
3580 ; CM-NEXT:    Fetch clause starting at 56:
3581 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 57, #3
3582 ; CM-NEXT:    Fetch clause starting at 58:
3583 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 53, #3
3584 ; CM-NEXT:    Fetch clause starting at 60:
3585 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 64, #3
3586 ; CM-NEXT:    Fetch clause starting at 62:
3587 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 60, #3
3588 ; CM-NEXT:    Fetch clause starting at 64:
3589 ; CM-NEXT:     VTX_READ_8 T8.X, T7.X, 56, #3
3590 ; CM-NEXT:    Fetch clause starting at 66:
3591 ; CM-NEXT:     VTX_READ_8 T7.X, T7.X, 52, #3
3592 ; CM-NEXT:    ALU clause starting at 68:
3593 ; CM-NEXT:     MOV * T0.Y, T2.X,
3594 ; CM-NEXT:     MOV * T7.X, 0.0,
3595 ; CM-NEXT:    ALU clause starting at 70:
3596 ; CM-NEXT:     LSHL T0.Z, T8.X, literal.x,
3597 ; CM-NEXT:     AND_INT * T0.W, T0.Y, literal.y,
3598 ; CM-NEXT:    24(3.363116e-44), 16777215(2.350989e-38)
3599 ; CM-NEXT:     OR_INT * T0.W, PV.W, PV.Z,
3600 ; CM-NEXT:     MOV T2.X, PV.W,
3601 ; CM-NEXT:     MOV * T0.Y, T3.X,
3602 ; CM-NEXT:    ALU clause starting at 76:
3603 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3604 ; CM-NEXT:     LSHL * T0.W, T8.X, literal.y,
3605 ; CM-NEXT:    16777215(2.350989e-38), 24(3.363116e-44)
3606 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3607 ; CM-NEXT:     MOV T3.X, PV.W,
3608 ; CM-NEXT:     MOV * T0.Y, T4.X,
3609 ; CM-NEXT:    ALU clause starting at 82:
3610 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3611 ; CM-NEXT:     LSHL * T0.W, T8.X, literal.y,
3612 ; CM-NEXT:    16777215(2.350989e-38), 24(3.363116e-44)
3613 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3614 ; CM-NEXT:     MOV T4.X, PV.W,
3615 ; CM-NEXT:     MOV * T0.Y, T5.X,
3616 ; CM-NEXT:    ALU clause starting at 88:
3617 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3618 ; CM-NEXT:     LSHL * T0.W, T8.X, literal.y,
3619 ; CM-NEXT:    16777215(2.350989e-38), 24(3.363116e-44)
3620 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3621 ; CM-NEXT:     MOV T5.X, PV.W,
3622 ; CM-NEXT:     MOV * T0.Y, T2.X,
3623 ; CM-NEXT:    ALU clause starting at 94:
3624 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.x,
3625 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
3626 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3627 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
3628 ; CM-NEXT:    -16711681(-1.714704e+38), 16(2.242078e-44)
3629 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3630 ; CM-NEXT:     MOV T2.X, PV.W,
3631 ; CM-NEXT:     MOV * T0.Y, T3.X,
3632 ; CM-NEXT:    ALU clause starting at 102:
3633 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.x,
3634 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
3635 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3636 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
3637 ; CM-NEXT:    -16711681(-1.714704e+38), 16(2.242078e-44)
3638 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3639 ; CM-NEXT:     MOV T3.X, PV.W,
3640 ; CM-NEXT:     MOV * T0.Y, T4.X,
3641 ; CM-NEXT:    ALU clause starting at 110:
3642 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.x,
3643 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
3644 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3645 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
3646 ; CM-NEXT:    -16711681(-1.714704e+38), 16(2.242078e-44)
3647 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3648 ; CM-NEXT:     MOV T4.X, PV.W,
3649 ; CM-NEXT:     MOV * T0.Y, T5.X,
3650 ; CM-NEXT:    ALU clause starting at 118:
3651 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.x,
3652 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
3653 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3654 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
3655 ; CM-NEXT:    -16711681(-1.714704e+38), 16(2.242078e-44)
3656 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3657 ; CM-NEXT:     MOV T5.X, PV.W,
3658 ; CM-NEXT:     MOV * T0.Y, T2.X,
3659 ; CM-NEXT:    ALU clause starting at 126:
3660 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.x,
3661 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
3662 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3663 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
3664 ; CM-NEXT:    -65281(nan), 8(1.121039e-44)
3665 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3666 ; CM-NEXT:     MOV T2.X, PV.W,
3667 ; CM-NEXT:     MOV * T0.Y, T3.X,
3668 ; CM-NEXT:    ALU clause starting at 134:
3669 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.x,
3670 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
3671 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3672 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
3673 ; CM-NEXT:    -65281(nan), 8(1.121039e-44)
3674 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3675 ; CM-NEXT:     MOV T3.X, PV.W,
3676 ; CM-NEXT:     MOV * T0.Y, T4.X,
3677 ; CM-NEXT:    ALU clause starting at 142:
3678 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.x,
3679 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
3680 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3681 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
3682 ; CM-NEXT:    -65281(nan), 8(1.121039e-44)
3683 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3684 ; CM-NEXT:     MOV T4.X, PV.W,
3685 ; CM-NEXT:     MOV * T0.Y, T5.X,
3686 ; CM-NEXT:    ALU clause starting at 150:
3687 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.x,
3688 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
3689 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3690 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.y,
3691 ; CM-NEXT:    -65281(nan), 8(1.121039e-44)
3692 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
3693 ; CM-NEXT:     MOV T5.X, PV.W,
3694 ; CM-NEXT:     MOV * T0.Y, T2.X,
3695 ; CM-NEXT:    ALU clause starting at 158:
3696 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3697 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.y,
3698 ; CM-NEXT:    -256(nan), 255(3.573311e-43)
3699 ; CM-NEXT:     OR_INT * T7.W, PV.Z, PV.W,
3700 ; CM-NEXT:     MOV T2.X, PV.W,
3701 ; CM-NEXT:     MOV * T0.Y, T3.X,
3702 ; CM-NEXT:    ALU clause starting at 164:
3703 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3704 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.y,
3705 ; CM-NEXT:    -256(nan), 255(3.573311e-43)
3706 ; CM-NEXT:     OR_INT * T7.Z, PV.Z, PV.W,
3707 ; CM-NEXT:     MOV T3.X, PV.Z,
3708 ; CM-NEXT:     MOV * T0.Y, T4.X,
3709 ; CM-NEXT:    ALU clause starting at 170:
3710 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3711 ; CM-NEXT:     AND_INT * T0.W, T8.X, literal.y,
3712 ; CM-NEXT:    -256(nan), 255(3.573311e-43)
3713 ; CM-NEXT:     OR_INT * T7.Y, PV.Z, PV.W,
3714 ; CM-NEXT:     MOV T4.X, PV.Y,
3715 ; CM-NEXT:     MOV * T0.Y, T5.X,
3716 ; CM-NEXT:    ALU clause starting at 176:
3717 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
3718 ; CM-NEXT:     AND_INT * T0.W, T7.X, literal.y,
3719 ; CM-NEXT:    -256(nan), 255(3.573311e-43)
3720 ; CM-NEXT:     OR_INT * T7.X, PV.Z, PV.W,
3721 ; CM-NEXT:     LSHR * T8.X, KC0[2].Y, literal.x,
3722 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
3985 ; CM-LABEL: v16i16_arg:
3986 ; CM:       ; %bb.0: ; %entry
3987 ; CM-NEXT:    ALU 1, @68, KC0[], KC1[]
3988 ; CM-NEXT:    TEX 0 @36
3989 ; CM-NEXT:    ALU 5, @70, KC0[], KC1[]
3990 ; CM-NEXT:    TEX 0 @38
3991 ; CM-NEXT:    ALU 5, @76, KC0[], KC1[]
3992 ; CM-NEXT:    TEX 0 @40
3993 ; CM-NEXT:    ALU 5, @82, KC0[], KC1[]
3994 ; CM-NEXT:    TEX 0 @42
3995 ; CM-NEXT:    ALU 5, @88, KC0[], KC1[]
3996 ; CM-NEXT:    TEX 0 @44
3997 ; CM-NEXT:    ALU 5, @94, KC0[], KC1[]
3998 ; CM-NEXT:    TEX 0 @46
3999 ; CM-NEXT:    ALU 5, @100, KC0[], KC1[]
4000 ; CM-NEXT:    TEX 0 @48
4001 ; CM-NEXT:    ALU 5, @106, KC0[], KC1[]
4002 ; CM-NEXT:    TEX 0 @50
4003 ; CM-NEXT:    ALU 5, @112, KC0[], KC1[]
4004 ; CM-NEXT:    TEX 0 @52
4005 ; CM-NEXT:    ALU 5, @118, KC0[], KC1[]
4006 ; CM-NEXT:    TEX 0 @54
4007 ; CM-NEXT:    ALU 5, @124, KC0[], KC1[]
4008 ; CM-NEXT:    TEX 0 @56
4009 ; CM-NEXT:    ALU 5, @130, KC0[], KC1[]
4010 ; CM-NEXT:    TEX 0 @58
4011 ; CM-NEXT:    ALU 5, @136, KC0[], KC1[]
4012 ; CM-NEXT:    TEX 0 @60
4013 ; CM-NEXT:    ALU 5, @142, KC0[], KC1[]
4014 ; CM-NEXT:    TEX 0 @62
4015 ; CM-NEXT:    ALU 5, @148, KC0[], KC1[]
4016 ; CM-NEXT:    TEX 0 @64
4017 ; CM-NEXT:    ALU 5, @154, KC0[], KC1[]
4018 ; CM-NEXT:    TEX 0 @66
4019 ; CM-NEXT:    ALU 14, @160, KC0[CB0:0-32], KC1[]
4020 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T11, T14.X
4021 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T12, T13.X
4022 ; CM-NEXT:    CF_END
4023 ; CM-NEXT:    Fetch clause starting at 36:
4024 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 98, #3
4025 ; CM-NEXT:    Fetch clause starting at 38:
4026 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 90, #3
4027 ; CM-NEXT:    Fetch clause starting at 40:
4028 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 82, #3
4029 ; CM-NEXT:    Fetch clause starting at 42:
4030 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 74, #3
4031 ; CM-NEXT:    Fetch clause starting at 44:
4032 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 96, #3
4033 ; CM-NEXT:    Fetch clause starting at 46:
4034 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 88, #3
4035 ; CM-NEXT:    Fetch clause starting at 48:
4036 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 80, #3
4037 ; CM-NEXT:    Fetch clause starting at 50:
4038 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 72, #3
4039 ; CM-NEXT:    Fetch clause starting at 52:
4040 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 94, #3
4041 ; CM-NEXT:    Fetch clause starting at 54:
4042 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 86, #3
4043 ; CM-NEXT:    Fetch clause starting at 56:
4044 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 78, #3
4045 ; CM-NEXT:    Fetch clause starting at 58:
4046 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 70, #3
4047 ; CM-NEXT:    Fetch clause starting at 60:
4048 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 92, #3
4049 ; CM-NEXT:    Fetch clause starting at 62:
4050 ; CM-NEXT:     VTX_READ_16 T12.X, T11.X, 84, #3
4051 ; CM-NEXT:    Fetch clause starting at 64:
4052 ; CM-NEXT:     VTX_READ_16 T13.X, T11.X, 76, #3
4053 ; CM-NEXT:    Fetch clause starting at 66:
4054 ; CM-NEXT:     VTX_READ_16 T11.X, T11.X, 68, #3
4055 ; CM-NEXT:    ALU clause starting at 68:
4056 ; CM-NEXT:     MOV * T0.Y, T3.X,
4057 ; CM-NEXT:     MOV * T11.X, 0.0,
4058 ; CM-NEXT:    ALU clause starting at 70:
4059 ; CM-NEXT:     LSHL T0.Z, T12.X, literal.x,
4060 ; CM-NEXT:     AND_INT * T0.W, T0.Y, literal.y,
4061 ; CM-NEXT:    16(2.242078e-44), 65535(9.183409e-41)
4062 ; CM-NEXT:     OR_INT * T0.W, PV.W, PV.Z,
4063 ; CM-NEXT:     MOV T3.X, PV.W,
4064 ; CM-NEXT:     MOV * T0.Y, T5.X,
4065 ; CM-NEXT:    ALU clause starting at 76:
4066 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4067 ; CM-NEXT:     LSHL * T0.W, T12.X, literal.y,
4068 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
4069 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4070 ; CM-NEXT:     MOV T5.X, PV.W,
4071 ; CM-NEXT:     MOV * T0.Y, T7.X,
4072 ; CM-NEXT:    ALU clause starting at 82:
4073 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4074 ; CM-NEXT:     LSHL * T0.W, T12.X, literal.y,
4075 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
4076 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4077 ; CM-NEXT:     MOV T7.X, PV.W,
4078 ; CM-NEXT:     MOV * T0.Y, T9.X,
4079 ; CM-NEXT:    ALU clause starting at 88:
4080 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4081 ; CM-NEXT:     LSHL * T0.W, T12.X, literal.y,
4082 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
4083 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4084 ; CM-NEXT:     MOV T9.X, PV.W,
4085 ; CM-NEXT:     MOV * T0.Y, T3.X,
4086 ; CM-NEXT:    ALU clause starting at 94:
4087 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4088 ; CM-NEXT:     AND_INT * T0.W, T12.X, literal.y,
4089 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
4090 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4091 ; CM-NEXT:     MOV T3.X, PV.W,
4092 ; CM-NEXT:     MOV * T0.Y, T5.X,
4093 ; CM-NEXT:    ALU clause starting at 100:
4094 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4095 ; CM-NEXT:     AND_INT * T0.W, T12.X, literal.y,
4096 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
4097 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4098 ; CM-NEXT:     MOV T5.X, PV.W,
4099 ; CM-NEXT:     MOV * T0.Y, T7.X,
4100 ; CM-NEXT:    ALU clause starting at 106:
4101 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4102 ; CM-NEXT:     AND_INT * T0.W, T12.X, literal.y,
4103 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
4104 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4105 ; CM-NEXT:     MOV T7.X, PV.W,
4106 ; CM-NEXT:     MOV * T0.Y, T9.X,
4107 ; CM-NEXT:    ALU clause starting at 112:
4108 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4109 ; CM-NEXT:     AND_INT * T0.W, T12.X, literal.y,
4110 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
4111 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4112 ; CM-NEXT:     MOV T9.X, PV.W,
4113 ; CM-NEXT:     MOV * T0.Y, T2.X,
4114 ; CM-NEXT:    ALU clause starting at 118:
4115 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4116 ; CM-NEXT:     LSHL * T0.W, T12.X, literal.y,
4117 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
4118 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4119 ; CM-NEXT:     MOV T2.X, PV.W,
4120 ; CM-NEXT:     MOV * T0.Y, T4.X,
4121 ; CM-NEXT:    ALU clause starting at 124:
4122 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4123 ; CM-NEXT:     LSHL * T0.W, T12.X, literal.y,
4124 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
4125 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4126 ; CM-NEXT:     MOV T4.X, PV.W,
4127 ; CM-NEXT:     MOV * T0.Y, T6.X,
4128 ; CM-NEXT:    ALU clause starting at 130:
4129 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4130 ; CM-NEXT:     LSHL * T0.W, T12.X, literal.y,
4131 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
4132 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4133 ; CM-NEXT:     MOV T6.X, PV.W,
4134 ; CM-NEXT:     MOV * T0.Y, T8.X,
4135 ; CM-NEXT:    ALU clause starting at 136:
4136 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4137 ; CM-NEXT:     LSHL * T0.W, T12.X, literal.y,
4138 ; CM-NEXT:    65535(9.183409e-41), 16(2.242078e-44)
4139 ; CM-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
4140 ; CM-NEXT:     MOV T8.X, PV.W,
4141 ; CM-NEXT:     MOV * T0.Y, T2.X,
4142 ; CM-NEXT:    ALU clause starting at 142:
4143 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4144 ; CM-NEXT:     AND_INT * T0.W, T12.X, literal.y,
4145 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
4146 ; CM-NEXT:     OR_INT * T12.Z, PV.Z, PV.W,
4147 ; CM-NEXT:     MOV T2.X, PV.Z,
4148 ; CM-NEXT:     MOV * T0.Y, T4.X,
4149 ; CM-NEXT:    ALU clause starting at 148:
4150 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4151 ; CM-NEXT:     AND_INT * T0.W, T12.X, literal.y,
4152 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
4153 ; CM-NEXT:     OR_INT * T12.X, PV.Z, PV.W,
4154 ; CM-NEXT:     MOV T4.X, PV.X,
4155 ; CM-NEXT:     MOV * T0.Y, T6.X,
4156 ; CM-NEXT:    ALU clause starting at 154:
4157 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.x,
4158 ; CM-NEXT:     AND_INT * T0.W, T13.X, literal.y,
4159 ; CM-NEXT:    -65536(nan), 65535(9.183409e-41)
4160 ; CM-NEXT:     OR_INT * T11.Z, PV.Z, PV.W,
4161 ; CM-NEXT:     MOV T6.X, PV.Z,
4162 ; CM-NEXT:     MOV * T0.Y, T8.X,
4163 ; CM-NEXT:    ALU clause starting at 160:
4164 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
4165 ; CM-NEXT:    16(2.242078e-44), 0(0.000000e+00)
4166 ; CM-NEXT:     LSHR * T13.X, PV.W, literal.x,
4167 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4168 ; CM-NEXT:     LSHR T14.X, KC0[2].Y, literal.x,
4169 ; CM-NEXT:     AND_INT T0.Z, T0.Y, literal.y,
4170 ; CM-NEXT:     AND_INT * T0.W, T11.X, literal.z,
4171 ; CM-NEXT:    2(2.802597e-45), -65536(nan)
4172 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
4173 ; CM-NEXT:     OR_INT * T11.X, PV.Z, PV.W,
4174 ; CM-NEXT:     MOV T8.X, PV.X,
4175 ; CM-NEXT:     MOV * T12.W, T3.X,
4176 ; CM-NEXT:     MOV T12.Y, T5.X,
4177 ; CM-NEXT:     MOV * T11.W, T7.X, BS:VEC_120/SCL_212
4178 ; CM-NEXT:     MOV * T11.Y, T9.X,
4329 ; CM-LABEL: v16i32_arg:
4330 ; CM:       ; %bb.0: ; %entry
4331 ; CM-NEXT:    ALU 28, @6, KC0[CB0:0-32], KC1[]
4332 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T4, T7.X
4333 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T6.X
4334 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T5.X
4335 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
4336 ; CM-NEXT:    CF_END
4337 ; CM-NEXT:    ALU clause starting at 6:
4338 ; CM-NEXT:     MOV * T0.W, KC0[10].X,
4339 ; CM-NEXT:     MOV * T0.Z, KC0[9].W,
4340 ; CM-NEXT:     MOV * T0.Y, KC0[9].Z,
4341 ; CM-NEXT:     MOV T0.X, KC0[9].Y,
4342 ; CM-NEXT:     ADD_INT T1.Z, KC0[2].Y, literal.x,
4343 ; CM-NEXT:     MOV * T2.W, KC0[9].X,
4344 ; CM-NEXT:    48(6.726233e-44), 0(0.000000e+00)
4345 ; CM-NEXT:     MOV T2.Z, KC0[8].W,
4346 ; CM-NEXT:     MOV * T1.W, KC0[8].X,
4347 ; CM-NEXT:     LSHR T3.X, T1.Z, literal.x,
4348 ; CM-NEXT:     MOV T2.Y, KC0[8].Z,
4349 ; CM-NEXT:     MOV * T1.Z, KC0[7].W,
4350 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4351 ; CM-NEXT:     MOV T2.X, KC0[8].Y,
4352 ; CM-NEXT:     MOV * T1.Y, KC0[7].Z,
4353 ; CM-NEXT:     MOV T1.X, KC0[7].Y,
4354 ; CM-NEXT:     ADD_INT T3.Z, KC0[2].Y, literal.x,
4355 ; CM-NEXT:     MOV * T4.W, KC0[7].X,
4356 ; CM-NEXT:    32(4.484155e-44), 0(0.000000e+00)
4357 ; CM-NEXT:     LSHR T5.X, PV.Z, literal.x,
4358 ; CM-NEXT:     MOV T4.Z, KC0[6].W,
4359 ; CM-NEXT:     ADD_INT * T3.W, KC0[2].Y, literal.y,
4360 ; CM-NEXT:    2(2.802597e-45), 16(2.242078e-44)
4361 ; CM-NEXT:     LSHR T6.X, PV.W, literal.x,
4362 ; CM-NEXT:     MOV * T4.Y, KC0[6].Z,
4363 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4364 ; CM-NEXT:     MOV * T4.X, KC0[6].Y,
4365 ; CM-NEXT:     LSHR * T7.X, KC0[2].Y, literal.x,
4366 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4517 ; CM-LABEL: v16f32_arg:
4518 ; CM:       ; %bb.0: ; %entry
4519 ; CM-NEXT:    ALU 28, @6, KC0[CB0:0-32], KC1[]
4520 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T4, T7.X
4521 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T6.X
4522 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T5.X
4523 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
4524 ; CM-NEXT:    CF_END
4525 ; CM-NEXT:    ALU clause starting at 6:
4526 ; CM-NEXT:     MOV * T0.W, KC0[10].X,
4527 ; CM-NEXT:     MOV * T0.Z, KC0[9].W,
4528 ; CM-NEXT:     MOV * T0.Y, KC0[9].Z,
4529 ; CM-NEXT:     MOV T0.X, KC0[9].Y,
4530 ; CM-NEXT:     ADD_INT T1.Z, KC0[2].Y, literal.x,
4531 ; CM-NEXT:     MOV * T2.W, KC0[9].X,
4532 ; CM-NEXT:    48(6.726233e-44), 0(0.000000e+00)
4533 ; CM-NEXT:     MOV T2.Z, KC0[8].W,
4534 ; CM-NEXT:     MOV * T1.W, KC0[8].X,
4535 ; CM-NEXT:     LSHR T3.X, T1.Z, literal.x,
4536 ; CM-NEXT:     MOV T2.Y, KC0[8].Z,
4537 ; CM-NEXT:     MOV * T1.Z, KC0[7].W,
4538 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4539 ; CM-NEXT:     MOV T2.X, KC0[8].Y,
4540 ; CM-NEXT:     MOV * T1.Y, KC0[7].Z,
4541 ; CM-NEXT:     MOV T1.X, KC0[7].Y,
4542 ; CM-NEXT:     ADD_INT T3.Z, KC0[2].Y, literal.x,
4543 ; CM-NEXT:     MOV * T4.W, KC0[7].X,
4544 ; CM-NEXT:    32(4.484155e-44), 0(0.000000e+00)
4545 ; CM-NEXT:     LSHR T5.X, PV.Z, literal.x,
4546 ; CM-NEXT:     MOV T4.Z, KC0[6].W,
4547 ; CM-NEXT:     ADD_INT * T3.W, KC0[2].Y, literal.y,
4548 ; CM-NEXT:    2(2.802597e-45), 16(2.242078e-44)
4549 ; CM-NEXT:     LSHR T6.X, PV.W, literal.x,
4550 ; CM-NEXT:     MOV * T4.Y, KC0[6].Z,
4551 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4552 ; CM-NEXT:     MOV * T4.X, KC0[6].Y,
4553 ; CM-NEXT:     LSHR * T7.X, KC0[2].Y, literal.x,
4554 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4607 ; CM-LABEL: kernel_arg_i64:
4608 ; CM:       ; %bb.0:
4609 ; CM-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
4610 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
4611 ; CM-NEXT:    CF_END
4612 ; CM-NEXT:    PAD
4613 ; CM-NEXT:    ALU clause starting at 4:
4614 ; CM-NEXT:     MOV * T0.Y, KC0[3].X,
4615 ; CM-NEXT:     MOV * T0.X, KC0[2].W,
4616 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
4617 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4669 ; CM-LABEL: f64_kernel_arg:
4670 ; CM:       ; %bb.0: ; %entry
4671 ; CM-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
4672 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
4673 ; CM-NEXT:    CF_END
4674 ; CM-NEXT:    PAD
4675 ; CM-NEXT:    ALU clause starting at 4:
4676 ; CM-NEXT:     MOV * T0.Y, KC0[3].X,
4677 ; CM-NEXT:     MOV * T0.X, KC0[2].W,
4678 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
4679 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4777 ; CM-LABEL: i65_arg:
4778 ; CM:       ; %bb.0: ; %entry
4779 ; CM-NEXT:    ALU 21, @6, KC0[CB0:0-32], KC1[]
4780 ; CM-NEXT:    MEM_RAT MSKOR T1.XW, T5.X
4781 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T4.X, T3.X
4782 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T0.X
4783 ; CM-NEXT:    CF_END
4784 ; CM-NEXT:    PAD
4785 ; CM-NEXT:    ALU clause starting at 6:
4786 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
4787 ; CM-NEXT:    8(1.121039e-44), 0(0.000000e+00)
4788 ; CM-NEXT:     AND_INT * T1.W, PV.W, literal.x,
4789 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
4790 ; CM-NEXT:     LSHL T0.Z, PV.W, literal.x,
4791 ; CM-NEXT:     AND_INT * T1.W, KC0[3].Y, 1,
4792 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
4793 ; CM-NEXT:     LSHL T1.X, PV.W, PV.Z,
4794 ; CM-NEXT:     LSHL * T1.W, literal.x, PV.Z,
4795 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
4796 ; CM-NEXT:     MOV T1.Y, 0.0,
4797 ; CM-NEXT:     MOV * T1.Z, 0.0,
4798 ; CM-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
4799 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4800 ; CM-NEXT:     MOV T2.X, KC0[2].W,
4801 ; CM-NEXT:     ADD_INT * T2.W, KC0[2].Y, literal.x,
4802 ; CM-NEXT:    4(5.605194e-45), 0(0.000000e+00)
4803 ; CM-NEXT:     LSHR * T3.X, PV.W, literal.x,
4804 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4805 ; CM-NEXT:     MOV * T4.X, KC0[3].X,
4806 ; CM-NEXT:     LSHR * T5.X, T0.W, literal.x,
4807 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4875 ; CM-LABEL: i1_arg:
4876 ; CM:       ; %bb.0:
4877 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
4878 ; CM-NEXT:    TEX 0 @6
4879 ; CM-NEXT:    ALU 11, @9, KC0[CB0:0-32], KC1[]
4880 ; CM-NEXT:    MEM_RAT MSKOR T0.XW, T1.X
4881 ; CM-NEXT:    CF_END
4882 ; CM-NEXT:    PAD
4883 ; CM-NEXT:    Fetch clause starting at 6:
4884 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 40, #3
4885 ; CM-NEXT:    ALU clause starting at 8:
4886 ; CM-NEXT:     MOV * T0.X, 0.0,
4887 ; CM-NEXT:    ALU clause starting at 9:
4888 ; CM-NEXT:     AND_INT * T0.W, KC0[2].Y, literal.x,
4889 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
4890 ; CM-NEXT:     AND_INT T0.Z, T0.X, 1,
4891 ; CM-NEXT:     LSHL * T0.W, PV.W, literal.x,
4892 ; CM-NEXT:    3(4.203895e-45), 0(0.000000e+00)
4893 ; CM-NEXT:     LSHL T0.X, PV.Z, PV.W,
4894 ; CM-NEXT:     LSHL * T0.W, literal.x, PV.W,
4895 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
4896 ; CM-NEXT:     MOV T0.Y, 0.0,
4897 ; CM-NEXT:     MOV * T0.Z, 0.0,
4898 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
4899 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
4956 ; CM-LABEL: i1_arg_zext_i32:
4957 ; CM:       ; %bb.0:
4958 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
4959 ; CM-NEXT:    TEX 0 @6
4960 ; CM-NEXT:    ALU 1, @9, KC0[CB0:0-32], KC1[]
4961 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
4962 ; CM-NEXT:    CF_END
4963 ; CM-NEXT:    PAD
4964 ; CM-NEXT:    Fetch clause starting at 6:
4965 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 40, #3
4966 ; CM-NEXT:    ALU clause starting at 8:
4967 ; CM-NEXT:     MOV * T0.X, 0.0,
4968 ; CM-NEXT:    ALU clause starting at 9:
4969 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
4970 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
5031 ; CM-LABEL: i1_arg_zext_i64:
5032 ; CM:       ; %bb.0:
5033 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
5034 ; CM-NEXT:    TEX 0 @6
5035 ; CM-NEXT:    ALU 2, @9, KC0[CB0:0-32], KC1[]
5036 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
5037 ; CM-NEXT:    CF_END
5038 ; CM-NEXT:    PAD
5039 ; CM-NEXT:    Fetch clause starting at 6:
5040 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 40, #3
5041 ; CM-NEXT:    ALU clause starting at 8:
5042 ; CM-NEXT:     MOV * T0.X, 0.0,
5043 ; CM-NEXT:    ALU clause starting at 9:
5044 ; CM-NEXT:     MOV * T0.Y, 0.0,
5045 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
5046 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
5105 ; CM-LABEL: i1_arg_sext_i32:
5106 ; CM:       ; %bb.0:
5107 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
5108 ; CM-NEXT:    TEX 0 @6
5109 ; CM-NEXT:    ALU 2, @9, KC0[CB0:0-32], KC1[]
5110 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
5111 ; CM-NEXT:    CF_END
5112 ; CM-NEXT:    PAD
5113 ; CM-NEXT:    Fetch clause starting at 6:
5114 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 40, #3
5115 ; CM-NEXT:    ALU clause starting at 8:
5116 ; CM-NEXT:     MOV * T0.X, 0.0,
5117 ; CM-NEXT:    ALU clause starting at 9:
5118 ; CM-NEXT:     BFE_INT * T0.X, T0.X, 0.0, 1,
5119 ; CM-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
5120 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
5183 ; CM-LABEL: i1_arg_sext_i64:
5184 ; CM:       ; %bb.0:
5185 ; CM-NEXT:    ALU 0, @8, KC0[], KC1[]
5186 ; CM-NEXT:    TEX 0 @6
5187 ; CM-NEXT:    ALU 3, @9, KC0[CB0:0-32], KC1[]
5188 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
5189 ; CM-NEXT:    CF_END
5190 ; CM-NEXT:    PAD
5191 ; CM-NEXT:    Fetch clause starting at 6:
5192 ; CM-NEXT:     VTX_READ_8 T0.X, T0.X, 40, #3
5193 ; CM-NEXT:    ALU clause starting at 8:
5194 ; CM-NEXT:     MOV * T0.X, 0.0,
5195 ; CM-NEXT:    ALU clause starting at 9:
5196 ; CM-NEXT:     BFE_INT * T0.X, T0.X, 0.0, 1,
5197 ; CM-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
5198 ; CM-NEXT:     MOV * T0.Y, PV.X,
5199 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
5335 ; CM-LABEL: struct_argument_alignment:
5336 ; CM:       ; %bb.0:
5337 ; CM-NEXT:    ALU 9, @8, KC0[CB0:0-32], KC1[]
5338 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T7.X, T6.X
5339 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T5.X, T4.X
5340 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T3.X, T6.X
5341 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T6.X
5342 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T4.X
5343 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T6.X
5344 ; CM-NEXT:    CF_END
5345 ; CM-NEXT:    ALU clause starting at 8:
5346 ; CM-NEXT:     MOV * T0.X, KC0[4].Y,
5347 ; CM-NEXT:     MOV * T1.X, KC0[4].Z,
5348 ; CM-NEXT:     MOV * T2.X, KC0[3].W,
5349 ; CM-NEXT:     MOV * T3.X, KC0[2].W,
5350 ; CM-NEXT:     MOV * T4.X, literal.x,
5351 ; CM-NEXT:    1(1.401298e-45), 0(0.000000e+00)
5352 ; CM-NEXT:     MOV * T5.X, KC0[3].X,
5353 ; CM-NEXT:     MOV * T6.X, literal.x,
5354 ; CM-NEXT:    0(0.000000e+00), 0(0.000000e+00)
5355 ; CM-NEXT:     MOV * T7.X, KC0[2].Y,
5509 ; CM-LABEL: packed_struct_argument_alignment:
5510 ; CM:       ; %bb.0:
5511 ; CM-NEXT:    ALU 6, @18, KC0[CB0:0-32], KC1[]
5512 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T4.X, T3.X
5513 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X
5514 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T3.X
5515 ; CM-NEXT:    ALU 2, @25, KC0[], KC1[]
5516 ; CM-NEXT:    TEX 0 @12
5517 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T3.X
5518 ; CM-NEXT:    TEX 0 @14
5519 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T1.X
5520 ; CM-NEXT:    TEX 0 @16
5521 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T4.X, T3.X
5522 ; CM-NEXT:    CF_END
5523 ; CM-NEXT:    Fetch clause starting at 12:
5524 ; CM-NEXT:     VTX_READ_32 T0.X, T0.X, 49, #3
5525 ; CM-NEXT:    Fetch clause starting at 14:
5526 ; CM-NEXT:     VTX_READ_32 T2.X, T2.X, 57, #3
5527 ; CM-NEXT:    Fetch clause starting at 16:
5528 ; CM-NEXT:     VTX_READ_32 T4.X, T4.X, 53, #3
5529 ; CM-NEXT:    ALU clause starting at 18:
5530 ; CM-NEXT:     MOV * T0.X, KC0[2].Z,
5531 ; CM-NEXT:     MOV * T1.X, literal.x,
5532 ; CM-NEXT:    1(1.401298e-45), 0(0.000000e+00)
5533 ; CM-NEXT:     MOV * T2.X, KC0[2].W,
5534 ; CM-NEXT:     MOV * T3.X, literal.x,
5535 ; CM-NEXT:    0(0.000000e+00), 0(0.000000e+00)
5536 ; CM-NEXT:     MOV * T4.X, KC0[2].Y,
5537 ; CM-NEXT:    ALU clause starting at 25:
5538 ; CM-NEXT:     MOV * T0.X, 0.0,
5539 ; CM-NEXT:     MOV * T2.X, 0.0,
5540 ; CM-NEXT:     MOV * T4.X, 0.0,
5679 ; CM-LABEL: struct_argument_alignment_after:
5680 ; CM:       ; %bb.0:
5681 ; CM-NEXT:    ALU 13, @10, KC0[CB0:0-32], KC1[]
5682 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T8.X, T7.X
5683 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T6.X, T5.X
5684 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T4.X, T7.X
5685 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T3.X, T7.X
5686 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T5.X
5687 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T7.X
5688 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T7.X
5689 ; CM-NEXT:    CF_END
5690 ; CM-NEXT:    PAD
5691 ; CM-NEXT:    ALU clause starting at 10:
5692 ; CM-NEXT:     MOV * T0.W, KC0[6].X,
5693 ; CM-NEXT:     MOV * T0.Z, KC0[5].W,
5694 ; CM-NEXT:     MOV * T0.Y, KC0[5].Z,
5695 ; CM-NEXT:     MOV * T0.X, KC0[5].Y,
5696 ; CM-NEXT:     MOV * T1.X, KC0[4].Y,
5697 ; CM-NEXT:     MOV * T2.X, KC0[4].Z,
5698 ; CM-NEXT:     MOV * T3.X, KC0[3].W,
5699 ; CM-NEXT:     MOV * T4.X, KC0[2].W,
5700 ; CM-NEXT:     MOV * T5.X, literal.x,
5701 ; CM-NEXT:    1(1.401298e-45), 0(0.000000e+00)
5702 ; CM-NEXT:     MOV * T6.X, KC0[3].X,
5703 ; CM-NEXT:     MOV * T7.X, literal.x,
5704 ; CM-NEXT:    0(0.000000e+00), 0(0.000000e+00)
5705 ; CM-NEXT:     MOV * T8.X, KC0[2].Y,
5810 ; CM-LABEL: array_3xi32:
5811 ; CM:       ; %bb.0:
5812 ; CM-NEXT:    ALU 0, @10, KC0[], KC1[]
5813 ; CM-NEXT:    TEX 0 @8
5814 ; CM-NEXT:    ALU 9, @11, KC0[CB0:0-32], KC1[]
5815 ; CM-NEXT:    MEM_RAT MSKOR T0.XW, T4.X
5816 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T3.X, T4.X
5817 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2.X, T4.X
5818 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T4.X
5819 ; CM-NEXT:    CF_END
5820 ; CM-NEXT:    Fetch clause starting at 8:
5821 ; CM-NEXT:     VTX_READ_16 T0.X, T0.X, 36, #3
5822 ; CM-NEXT:    ALU clause starting at 10:
5823 ; CM-NEXT:     MOV * T0.X, 0.0,
5824 ; CM-NEXT:    ALU clause starting at 11:
5825 ; CM-NEXT:     AND_INT T0.X, T0.X, literal.x,
5826 ; CM-NEXT:     MOV * T0.W, literal.x,
5827 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
5828 ; CM-NEXT:     MOV T0.Y, 0.0,
5829 ; CM-NEXT:     MOV * T0.Z, 0.0,
5830 ; CM-NEXT:     MOV * T1.X, KC0[2].Z,
5831 ; CM-NEXT:     MOV * T2.X, KC0[2].W,
5832 ; CM-NEXT:     MOV * T3.X, KC0[3].X,
5833 ; CM-NEXT:     MOV * T4.X, literal.x,
5834 ; CM-NEXT:    0(0.000000e+00), 0(0.000000e+00)
5960 ; CM-LABEL: array_3xi16:
5961 ; CM:       ; %bb.0:
5962 ; CM-NEXT:    ALU 0, @20, KC0[], KC1[]
5963 ; CM-NEXT:    TEX 1 @12
5964 ; CM-NEXT:    ALU 11, @21, KC0[], KC1[]
5965 ; CM-NEXT:    MEM_RAT MSKOR T1.XW, T3.X
5966 ; CM-NEXT:    MEM_RAT MSKOR T2.XW, T3.X
5967 ; CM-NEXT:    TEX 0 @16
5968 ; CM-NEXT:    ALU 3, @33, KC0[], KC1[]
5969 ; CM-NEXT:    MEM_RAT MSKOR T2.XW, T3.X
5970 ; CM-NEXT:    TEX 0 @18
5971 ; CM-NEXT:    ALU 3, @37, KC0[], KC1[]
5972 ; CM-NEXT:    MEM_RAT MSKOR T2.XW, T3.X
5973 ; CM-NEXT:    CF_END
5974 ; CM-NEXT:    Fetch clause starting at 12:
5975 ; CM-NEXT:     VTX_READ_8 T1.X, T0.X, 36, #3
5976 ; CM-NEXT:     VTX_READ_16 T2.X, T0.X, 42, #3
5977 ; CM-NEXT:    Fetch clause starting at 16:
5978 ; CM-NEXT:     VTX_READ_16 T1.X, T0.X, 40, #3
5979 ; CM-NEXT:    Fetch clause starting at 18:
5980 ; CM-NEXT:     VTX_READ_16 T0.X, T0.X, 38, #3
5981 ; CM-NEXT:    ALU clause starting at 20:
5982 ; CM-NEXT:     MOV * T0.X, 0.0,
5983 ; CM-NEXT:    ALU clause starting at 21:
5984 ; CM-NEXT:     AND_INT T1.X, T1.X, literal.x,
5985 ; CM-NEXT:     MOV * T1.W, literal.x,
5986 ; CM-NEXT:    255(3.573311e-43), 0(0.000000e+00)
5987 ; CM-NEXT:     MOV * T1.Y, 0.0,
5988 ; CM-NEXT:     AND_INT T2.X, T2.X, literal.x,
5989 ; CM-NEXT:     MOV * T2.W, literal.x,
5990 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
5991 ; CM-NEXT:     MOV T2.Y, 0.0,
5992 ; CM-NEXT:     MOV * T1.Z, 0.0,
5993 ; CM-NEXT:     MOV * T2.Z, 0.0,
5994 ; CM-NEXT:     MOV * T3.X, literal.x,
5995 ; CM-NEXT:    0(0.000000e+00), 0(0.000000e+00)
5996 ; CM-NEXT:    ALU clause starting at 33:
5997 ; CM-NEXT:     AND_INT T2.X, T1.X, literal.x,
5998 ; CM-NEXT:     MOV T2.Y, 0.0,
5999 ; CM-NEXT:     MOV * T2.Z, 0.0,
6000 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
6001 ; CM-NEXT:    ALU clause starting at 37:
6002 ; CM-NEXT:     AND_INT T2.X, T0.X, literal.x,
6003 ; CM-NEXT:     MOV T2.Y, 0.0,
6004 ; CM-NEXT:     MOV * T2.Z, 0.0,
6005 ; CM-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
6130 ; CM-LABEL: byref_align_constant_i32_arg:
6131 ; CM:       ; %bb.0:
6132 ; CM-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
6133 ; CM-NEXT:    TEX 0 @6
6134 ; CM-NEXT:    ALU 2, @9, KC0[CB0:0-32], KC1[]
6135 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0.X, T2.X
6136 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X
6137 ; CM-NEXT:    CF_END
6138 ; CM-NEXT:    Fetch clause starting at 6:
6139 ; CM-NEXT:     VTX_READ_32 T0.X, T0.X, 0, #1
6140 ; CM-NEXT:    ALU clause starting at 8:
6141 ; CM-NEXT:     MOV * T0.X, KC0[18].Y,
6142 ; CM-NEXT:    ALU clause starting at 9:
6143 ; CM-NEXT:     MOV * T1.X, KC0[18].Z,
6144 ; CM-NEXT:     LSHR * T2.X, KC0[2].Y, literal.x,
6145 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
6323 ; CM-LABEL: byref_natural_align_constant_v16i32_arg:
6324 ; CM:       ; %bb.0:
6325 ; CM-NEXT:    ALU 0, @24, KC0[CB0:0-32], KC1[]
6326 ; CM-NEXT:    TEX 0 @16
6327 ; CM-NEXT:    ALU 3, @25, KC0[CB0:0-32], KC1[]
6328 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1, T2.X
6329 ; CM-NEXT:    ALU 3, @29, KC0[CB0:0-32], KC1[]
6330 ; CM-NEXT:    TEX 0 @18
6331 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T1.X
6332 ; CM-NEXT:    ALU 3, @33, KC0[CB0:0-32], KC1[]
6333 ; CM-NEXT:    TEX 0 @20
6334 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T2, T1.X
6335 ; CM-NEXT:    ALU 2, @37, KC0[CB0:0-32], KC1[]
6336 ; CM-NEXT:    TEX 0 @22
6337 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T0, T2.X
6338 ; CM-NEXT:    MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X
6339 ; CM-NEXT:    CF_END
6340 ; CM-NEXT:    PAD
6341 ; CM-NEXT:    Fetch clause starting at 16:
6342 ; CM-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 48, #1
6343 ; CM-NEXT:    Fetch clause starting at 18:
6344 ; CM-NEXT:     VTX_READ_128 T2.XYZW, T0.X, 32, #1
6345 ; CM-NEXT:    Fetch clause starting at 20:
6346 ; CM-NEXT:     VTX_READ_128 T2.XYZW, T0.X, 16, #1
6347 ; CM-NEXT:    Fetch clause starting at 22:
6348 ; CM-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
6349 ; CM-NEXT:    ALU clause starting at 24:
6350 ; CM-NEXT:     MOV * T0.X, KC0[6].Y,
6351 ; CM-NEXT:    ALU clause starting at 25:
6352 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
6353 ; CM-NEXT:    48(6.726233e-44), 0(0.000000e+00)
6354 ; CM-NEXT:     LSHR * T2.X, PV.W, literal.x,
6355 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
6356 ; CM-NEXT:    ALU clause starting at 29:
6357 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
6358 ; CM-NEXT:    32(4.484155e-44), 0(0.000000e+00)
6359 ; CM-NEXT:     LSHR * T1.X, PV.W, literal.x,
6360 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
6361 ; CM-NEXT:    ALU clause starting at 33:
6362 ; CM-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
6363 ; CM-NEXT:    16(2.242078e-44), 0(0.000000e+00)
6364 ; CM-NEXT:     LSHR * T1.X, PV.W, literal.x,
6365 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)
6366 ; CM-NEXT:    ALU clause starting at 37:
6367 ; CM-NEXT:     MOV * T1.X, KC0[10].Y,
6368 ; CM-NEXT:     LSHR * T2.X, KC0[2].Y, literal.x,
6369 ; CM-NEXT:    2(2.802597e-45), 0(0.000000e+00)