Lines Matching refs:s7
22 ; GFX9-NEXT: s_mul_i32 s7, s5, s6
23 ; GFX9-NEXT: s_mul_hi_u32 s7, s6, s7
24 ; GFX9-NEXT: s_add_i32 s6, s6, s7
25 ; GFX9-NEXT: s_mul_i32 s7, s3, s6
27 ; GFX9-NEXT: s_add_i32 s6, s6, s7
28 ; GFX9-NEXT: s_mul_i32 s7, s5, s6
29 ; GFX9-NEXT: s_add_i32 s7, s2, s7
30 ; GFX9-NEXT: s_cmp_ge_u32 s7, s4
32 ; GFX9-NEXT: v_mov_b32_e32 v3, s7
34 ; GFX9-NEXT: s_add_i32 s7, s6, 1
37 ; GFX9-NEXT: v_mov_b32_e32 v4, s7
70 ; GFX10-NEXT: s_mul_i32 s7, s5, s6
71 ; GFX10-NEXT: s_mul_hi_u32 s7, s6, s7
72 ; GFX10-NEXT: s_add_i32 s6, s6, s7
73 ; GFX10-NEXT: s_mul_i32 s7, s3, s6
75 ; GFX10-NEXT: s_add_i32 s6, s6, s7
76 ; GFX10-NEXT: s_mul_i32 s7, s5, s6
77 ; GFX10-NEXT: s_add_i32 s7, s2, s7
78 ; GFX10-NEXT: s_cmp_ge_u32 s7, s4
89 ; GFX10-NEXT: v_cndmask_b32_e32 v3, s7, v3, vcc_lo
122 ; GFX11-NEXT: s_mul_i32 s7, s5, s6
124 ; GFX11-NEXT: s_mul_hi_u32 s7, s6, s7
125 ; GFX11-NEXT: s_add_i32 s6, s6, s7
127 ; GFX11-NEXT: s_mul_i32 s7, s3, s6
129 ; GFX11-NEXT: s_add_i32 s6, s6, s7
131 ; GFX11-NEXT: s_mul_i32 s7, s5, s6
132 ; GFX11-NEXT: s_add_i32 s7, s2, s7
134 ; GFX11-NEXT: s_cmp_ge_u32 s7, s4
146 ; GFX11-NEXT: v_dual_cndmask_b32 v3, s7, v3 :: v_dual_add_nc_u32 v4, 1, v2
191 ; GFX9-NEXT: s_mul_i32 s7, s5, s6
192 ; GFX9-NEXT: s_mul_hi_u32 s7, s6, s7
193 ; GFX9-NEXT: s_add_i32 s6, s6, s7
194 ; GFX9-NEXT: s_mul_i32 s7, s3, s6
196 ; GFX9-NEXT: s_add_i32 s6, s6, s7
197 ; GFX9-NEXT: s_mul_i32 s7, s5, s6
200 ; GFX9-NEXT: s_add_i32 s7, s2, s7
202 ; GFX9-NEXT: s_cmp_ge_u32 s7, s4
203 ; GFX9-NEXT: s_cselect_b32 s6, s6, s7
204 ; GFX9-NEXT: s_sub_i32 s7, s6, s4
206 ; GFX9-NEXT: s_cselect_b32 s6, s7, s6
233 ; GFX10-NEXT: s_mul_i32 s7, s5, s6
234 ; GFX10-NEXT: s_mul_hi_u32 s7, s6, s7
235 ; GFX10-NEXT: s_add_i32 s6, s6, s7
236 ; GFX10-NEXT: s_mul_i32 s7, s3, s6
238 ; GFX10-NEXT: s_add_i32 s6, s6, s7
239 ; GFX10-NEXT: s_not_b32 s7, s6
241 ; GFX10-NEXT: s_mul_i32 s7, s4, s7
243 ; GFX10-NEXT: s_add_i32 s7, s2, s7
245 ; GFX10-NEXT: s_cselect_b32 s6, s7, s6
246 ; GFX10-NEXT: s_sub_i32 s7, s6, s4
248 ; GFX10-NEXT: s_cselect_b32 s6, s7, s6
281 ; GFX11-NEXT: s_mul_i32 s7, s5, s6
283 ; GFX11-NEXT: s_mul_hi_u32 s7, s6, s7
284 ; GFX11-NEXT: s_add_i32 s6, s6, s7
286 ; GFX11-NEXT: s_mul_i32 s7, s3, s6
288 ; GFX11-NEXT: s_add_i32 s6, s6, s7
290 ; GFX11-NEXT: s_not_b32 s7, s6
292 ; GFX11-NEXT: s_mul_i32 s7, s4, s7
294 ; GFX11-NEXT: s_add_i32 s7, s2, s7
296 ; GFX11-NEXT: s_cselect_b32 s6, s7, s6
298 ; GFX11-NEXT: s_sub_i32 s7, s6, s4
300 ; GFX11-NEXT: s_cselect_b32 s6, s7, s6
391 ; GFX10-NEXT: s_mul_i32 s7, s5, s6
392 ; GFX10-NEXT: s_mul_hi_u32 s7, s6, s7
393 ; GFX10-NEXT: s_add_i32 s6, s6, s7
395 ; GFX10-NEXT: s_mul_i32 s7, s6, s3
396 ; GFX10-NEXT: s_sub_i32 s7, s4, s7
397 ; GFX10-NEXT: s_cmp_ge_u32 s7, s3
402 ; GFX10-NEXT: s_sub_i32 s8, s7, s3
405 ; GFX10-NEXT: v_cndmask_b32_e32 v3, s7, v3, vcc_lo
445 ; GFX11-NEXT: s_mul_i32 s7, s5, s6
447 ; GFX11-NEXT: s_mul_hi_u32 s7, s6, s7
448 ; GFX11-NEXT: s_add_i32 s6, s6, s7
451 ; GFX11-NEXT: s_mul_i32 s7, s6, s3
453 ; GFX11-NEXT: s_sub_i32 s7, s4, s7
454 ; GFX11-NEXT: s_cmp_ge_u32 s7, s3
459 ; GFX11-NEXT: s_sub_i32 s8, s7, s3
464 ; GFX11-NEXT: v_dual_cndmask_b32 v3, s7, v3 :: v_dual_add_nc_u32 v4, 1, v2
652 ; GFX9-NEXT: s_mov_b32 s7, 0
660 ; GFX9-NEXT: s_and_b32 s4, 0xffff, s7
662 ; GFX9-NEXT: v_add_u16_e64 v3, s7, 1
663 ; GFX9-NEXT: v_readfirstlane_b32 s7, v3
702 ; GFX10-NEXT: s_addc_u32 s7, s3, s5
740 ; GFX11-NEXT: s_addc_u32 s7, s3, s5
777 ; GFX9-NEXT: s_movk_i32 s7, 0x400
795 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s7, v4
914 ; GFX9-NEXT: s_xor_b32 s7, s2, s4
915 ; GFX9-NEXT: s_ashr_i32 s2, s7, 30
923 ; GFX9-NEXT: s_cselect_b32 s7, s2, 0
930 ; GFX9-NEXT: v_add_u32_e32 v3, s7, v5
970 ; GFX10-NEXT: s_addc_u32 s7, s3, s7
1016 ; GFX11-NEXT: s_addc_u32 s7, s1, s7
1054 ; GFX9-NEXT: s_sext_i32_i16 s7, s6
1055 ; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s7
1056 ; GFX9-NEXT: s_xor_b32 s2, s7, s4
1075 ; GFX9-NEXT: v_sub_u32_e32 v3, s7, v3
1115 ; GFX10-NEXT: s_addc_u32 s7, s3, s7
1165 ; GFX11-NEXT: s_addc_u32 s7, s1, s7