Lines Matching refs:DISABLED

4 …fiji -amdgpu-codegenprepare-mul24=0 -amdgpu-codegenprepare %s | FileCheck -check-prefix=DISABLED %s
18 ; DISABLED-LABEL: @mul_i16(
19 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
20 ; DISABLED-NEXT:    ret i16 [[MUL]]
43 ; DISABLED-LABEL: @smul24_i32(
44 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8
45 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8
46 ; DISABLED-NEXT:    [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 8
47 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 8
48 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
49 ; DISABLED-NEXT:    ret i32 [[MUL]]
90 ; DISABLED-LABEL: @smul24_v2i32(
91 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8>
92 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8>
93 ; DISABLED-NEXT:    [[SHL_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8>
94 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr <2 x i32> [[SHL_RHS]], <i32 8, i32 8>
95 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
96 ; DISABLED-NEXT:    ret <2 x i32> [[MUL]]
119 ; DISABLED-LABEL: @umul24_i32(
120 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215
121 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215
122 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
123 ; DISABLED-NEXT:    ret i32 [[MUL]]
158 ; DISABLED-LABEL: @umul24_v2i32(
159 ; DISABLED-NEXT:    [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215>
160 ; DISABLED-NEXT:    [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215>
161 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
162 ; DISABLED-NEXT:    ret <2 x i32> [[MUL]]
201 ; DISABLED-LABEL: @smul24_i64(
202 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40
203 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40
204 ; DISABLED-NEXT:    [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 40
205 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 40
206 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
207 ; DISABLED-NEXT:    ret i64 [[MUL]]
240 ; DISABLED-LABEL: @smul24_i64_2(
241 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 49
242 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 49
243 ; DISABLED-NEXT:    [[SHL_RHS:%.*]] = shl i64 [[RHS:%.*]], 49
244 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i64 [[SHL_RHS]], 49
245 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
246 ; DISABLED-NEXT:    ret i64 [[MUL]]
287 ; DISABLED-LABEL: @smul24_i64_3(
288 ; DISABLED-NEXT:    [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i16
289 ; DISABLED-NEXT:    [[LHS24:%.*]] = sext i16 [[LHS_TRUNC]] to i64
290 ; DISABLED-NEXT:    [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i17
291 ; DISABLED-NEXT:    [[RHS24:%.*]] = sext i17 [[RHS_TRUNC]] to i64
292 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
293 ; DISABLED-NEXT:    ret i64 [[MUL]]
320 ; DISABLED-LABEL: @smul24_i64_4(
321 ; DISABLED-NEXT:    [[LHS_TRUNC:%.*]] = trunc i64 [[LHS:%.*]] to i24
322 ; DISABLED-NEXT:    [[LHS24:%.*]] = sext i24 [[LHS_TRUNC]] to i64
323 ; DISABLED-NEXT:    [[RHS_TRUNC:%.*]] = trunc i64 [[RHS:%.*]] to i25
324 ; DISABLED-NEXT:    [[RHS24:%.*]] = sext i25 [[RHS_TRUNC]] to i64
325 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
326 ; DISABLED-NEXT:    ret i64 [[MUL]]
363 ; DISABLED-LABEL: @umul24_i64(
364 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215
365 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215
366 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
367 ; DISABLED-NEXT:    ret i64 [[MUL]]
394 ; DISABLED-LABEL: @umul24_i64_2(
395 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i64 [[LHS:%.*]], 65535
396 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i64 [[RHS:%.*]], 65535
397 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
398 ; DISABLED-NEXT:    ret i64 [[MUL]]
429 ; DISABLED-LABEL: @smul24_i31(
430 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7
431 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7
432 ; DISABLED-NEXT:    [[SHL_RHS:%.*]] = shl i31 [[RHS:%.*]], 7
433 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i31 [[SHL_RHS]], 7
434 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
435 ; DISABLED-NEXT:    ret i31 [[MUL]]
464 ; DISABLED-LABEL: @umul24_i31(
465 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215
466 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215
467 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
468 ; DISABLED-NEXT:    ret i31 [[MUL]]
515 ; DISABLED-LABEL: @umul24_v2i31(
516 ; DISABLED-NEXT:    [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215>
517 ; DISABLED-NEXT:    [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215>
518 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
519 ; DISABLED-NEXT:    ret <2 x i31> [[MUL]]
570 ; DISABLED-LABEL: @smul24_v2i31(
571 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8>
572 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8>
573 ; DISABLED-NEXT:    [[SHL_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8>
574 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr <2 x i31> [[SHL_RHS]], <i31 8, i31 8>
575 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
576 ; DISABLED-NEXT:    ret <2 x i31> [[MUL]]
619 ; DISABLED-LABEL: @smul24_i33(
620 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9
621 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9
622 ; DISABLED-NEXT:    [[SHL_RHS:%.*]] = shl i33 [[RHS:%.*]], 9
623 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i33 [[SHL_RHS]], 9
624 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
625 ; DISABLED-NEXT:    ret i33 [[MUL]]
664 ; DISABLED-LABEL: @umul24_i33(
665 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215
666 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215
667 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
668 ; DISABLED-NEXT:    ret i33 [[MUL]]
693 ; DISABLED-LABEL: @smul25_i32(
694 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7
695 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7
696 ; DISABLED-NEXT:    [[SHL_RHS:%.*]] = shl i32 [[RHS:%.*]], 7
697 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr i32 [[SHL_RHS]], 7
698 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
699 ; DISABLED-NEXT:    ret i32 [[MUL]]
722 ; DISABLED-LABEL: @umul25_i32(
723 ; DISABLED-NEXT:    [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431
724 ; DISABLED-NEXT:    [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431
725 ; DISABLED-NEXT:    [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
726 ; DISABLED-NEXT:    ret i32 [[MUL]]
797 ; DISABLED-LABEL: @smul24_v2i33(
798 ; DISABLED-NEXT:    [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9>
799 ; DISABLED-NEXT:    [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9>
800 ; DISABLED-NEXT:    [[SHL_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9>
801 ; DISABLED-NEXT:    [[RHS24:%.*]] = ashr <2 x i33> [[SHL_RHS]], <i33 9, i33 9>
802 ; DISABLED-NEXT:    [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]]
803 ; DISABLED-NEXT:    ret <2 x i33> [[MUL]]