Lines Matching refs:amount
8 define i8 @v_shl_i8(i8 %value, i8 %amount) {
35 %result = shl i8 %value, %amount
68 define amdgpu_ps i8 @s_shl_i8(i8 inreg %value, i8 inreg %amount) {
91 %result = shl i8 %value, %amount
123 define i24 @v_shl_i24(i24 %value, i24 %amount) {
138 %result = shl i24 %value, %amount
159 define amdgpu_ps i24 @s_shl_i24(i24 inreg %value, i24 inreg %amount) {
169 %result = shl i24 %value, %amount
187 define i32 @v_shl_i32(i32 %value, i32 %amount) {
200 %result = shl i32 %value, %amount
221 define amdgpu_ps i32 @s_shl_i32(i32 inreg %value, i32 inreg %amount) {
231 %result = shl i32 %value, %amount
249 define amdgpu_ps float @shl_i32_sv(i32 inreg %value, i32 %amount) {
269 %result = shl i32 %value, %amount
274 define amdgpu_ps float @shl_i32_vs(i32 %value, i32 inreg %amount) {
284 %result = shl i32 %value, %amount
289 define <2 x i32> @v_shl_v2i32(<2 x i32> %value, <2 x i32> %amount) {
304 %result = shl <2 x i32> %value, %amount
327 define amdgpu_ps <2 x i32> @s_shl_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) {
339 %result = shl <2 x i32> %value, %amount
343 define <3 x i32> @v_shl_v3i32(<3 x i32> %value, <3 x i32> %amount) {
360 %result = shl <3 x i32> %value, %amount
364 define amdgpu_ps <3 x i32> @s_shl_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) {
378 %result = shl <3 x i32> %value, %amount
382 define <4 x i32> @v_shl_v4i32(<4 x i32> %value, <4 x i32> %amount) {
401 %result = shl <4 x i32> %value, %amount
405 define amdgpu_ps <4 x i32> @s_shl_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) {
421 %result = shl <4 x i32> %value, %amount
425 define <5 x i32> @v_shl_v5i32(<5 x i32> %value, <5 x i32> %amount) {
446 %result = shl <5 x i32> %value, %amount
450 define amdgpu_ps <5 x i32> @s_shl_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) {
468 %result = shl <5 x i32> %value, %amount
472 define <16 x i32> @v_shl_v16i32(<16 x i32> %value, <16 x i32> %amount) {
543 %result = shl <16 x i32> %value, %amount
547 define amdgpu_ps <16 x i32> @s_shl_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {
587 %result = shl <16 x i32> %value, %amount
591 define i16 @v_shl_i16(i16 %value, i16 %amount) {
617 %result = shl i16 %value, %amount
636 define amdgpu_ps i16 @s_shl_i16(i16 inreg %value, i16 inreg %amount) {
659 %result = shl i16 %value, %amount
690 define amdgpu_ps half @shl_i16_sv(i16 inreg %value, i16 %amount) {
711 %result = shl i16 %value, %amount
716 define amdgpu_ps half @shl_i16_vs(i16 %value, i16 inreg %amount) {
737 %result = shl i16 %value, %amount
742 define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) {
772 %result = shl <2 x i16> %value, %amount
809 define amdgpu_ps i32 @s_shl_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {
849 %result = shl <2 x i16> %value, %amount
854 define amdgpu_ps float @shl_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
885 %result = shl <2 x i16> %value, %amount
890 define amdgpu_ps float @shl_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {
921 %result = shl <2 x i16> %value, %amount
927 ; define <3 x i16> @v_shl_v3i16(<3 x i16> %value, <3 x i16> %amount) {
928 ; %result = shl <3 x i16> %value, %amount
932 ; define amdgpu_ps <3 x i16> @s_shl_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) {
933 ; %result = shl <3 x i16> %value, %amount
937 define <2 x float> @v_shl_v4i16(<4 x i16> %value, <4 x i16> %amount) {
984 %result = shl <4 x i16> %value, %amount
989 define amdgpu_ps <2 x i32> @s_shl_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) {
1053 %result = shl <4 x i16> %value, %amount
1059 ; define <5 x i16> @v_shl_v5i16(<5 x i16> %value, <5 x i16> %amount) {
1060 ; %result = shl <5 x i16> %value, %amount
1064 ; define amdgpu_ps <5 x i16> @s_shl_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) {
1065 ; %result = shl <5 x i16> %value, %amount
1069 ; define <3 x float> @v_shl_v6i16(<6 x i16> %value, <6 x i16> %amount) {
1070 ; %result = shl <6 x i16> %value, %amount
1075 ; define amdgpu_ps <3 x i32> @s_shl_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) {
1076 ; %result = shl <6 x i16> %value, %amount
1081 define <4 x float> @v_shl_v8i16(<8 x i16> %value, <8 x i16> %amount) {
1154 %result = shl <8 x i16> %value, %amount
1159 define amdgpu_ps <4 x i32> @s_shl_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) {
1271 %result = shl <8 x i16> %value, %amount
1276 define i64 @v_shl_i64(i64 %value, i64 %amount) {
1301 %result = shl i64 %value, %amount
1412 define amdgpu_ps i64 @s_shl_i64(i64 inreg %value, i64 inreg %amount) {
1422 %result = shl i64 %value, %amount
1488 define amdgpu_ps <2 x float> @shl_i64_sv(i64 inreg %value, i64 %amount) {
1508 %result = shl i64 %value, %amount
1513 define amdgpu_ps <2 x float> @shl_i64_vs(i64 %value, i64 inreg %amount) {
1533 %result = shl i64 %value, %amount
1538 define <2 x i64> @v_shl_v2i64(<2 x i64> %value, <2 x i64> %amount) {
1567 %result = shl <2 x i64> %value, %amount
1604 define amdgpu_ps <2 x i64> @s_shl_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) {
1616 %result = shl <2 x i64> %value, %amount
1620 define i65 @v_shl_i65(i65 %value, i65 %amount) {
1711 %result = shl i65 %value, %amount
1765 define amdgpu_ps i65 @s_shl_i65(i65 inreg %value, i65 inreg %amount) {
1805 %result = shl i65 %value, %amount
1835 ; define <2 x i65> @v_shl_v2i65(<2 x i65> %value, <2 x i65> %amount) {
1836 ; %result = shl <2 x i65> %value, %amount
1840 ; define amdgpu_ps <2 x i65> @s_shl_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) {
1841 ; %result = shl <2 x i65> %value, %amount