Lines Matching refs:s7
11 ; GFX8-NEXT: s_ashr_i32 s8, s7, 31
12 ; GFX8-NEXT: s_add_i32 s0, s7, s8
13 ; GFX8-NEXT: s_xor_b32 s7, s0, s8
14 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s7
15 ; GFX8-NEXT: s_sub_i32 s0, 0, s7
31 ; GFX8-NEXT: v_mul_lo_u32 v3, v2, s7
34 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
36 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s7, v3
39 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
41 ; GFX8-NEXT: v_subrev_u32_e64 v4, s[0:1], s7, v3
60 ; GFX9-NEXT: s_xor_b32 s7, s1, s6
61 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
62 ; GFX9-NEXT: s_sub_i32 s1, 0, s7
75 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s7
78 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
80 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
83 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
85 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
104 ; GFX10-NEXT: s_xor_b32 s7, s1, s6
106 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s7
107 ; GFX10-NEXT: s_sub_i32 s1, 0, s7
115 ; GFX10-NEXT: v_mul_lo_u32 v1, v0, s7
120 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s7, v1
121 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s7, v1
125 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s7, v1
126 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s7, v1
303 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
696 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
706 ; GFX9-NEXT: s_xor_b32 s7, s0, s6
707 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
714 ; GFX9-NEXT: s_sub_i32 s11, 0, s7
733 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s7
738 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
740 ; GFX9-NEXT: v_subrev_u32_e32 v2, s7, v3
743 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
745 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v2
788 ; GFX10-NEXT: s_sub_i32 s7, 0, s3
802 ; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1
994 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
1004 ; GFX9-NEXT: s_xor_b32 s7, s0, s6
1005 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
1012 ; GFX9-NEXT: s_sub_i32 s13, 0, s7
1031 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s7
1036 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
1038 ; GFX9-NEXT: v_subrev_u32_e32 v2, s7, v3
1041 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
1043 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v2
1050 ; GFX9-NEXT: s_add_i32 s7, s14, s6
1052 ; GFX9-NEXT: s_xor_b32 s7, s7, s6
1055 ; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s7
1066 ; GFX9-NEXT: s_sub_i32 s8, 0, s7
1086 ; GFX9-NEXT: v_mul_lo_u32 v6, v3, s7
1094 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
1096 ; GFX9-NEXT: v_subrev_u32_e32 v6, s7, v2
1100 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
1102 ; GFX9-NEXT: v_subrev_u32_e32 v6, s7, v2
1103 ; GFX9-NEXT: s_ashr_i32 s7, s11, 31
1104 ; GFX9-NEXT: s_add_i32 s8, s11, s7
1105 ; GFX9-NEXT: s_xor_b32 s8, s8, s7
1113 ; GFX9-NEXT: s_xor_b32 s4, s7, s4
1128 ; GFX9-NEXT: v_xor_b32_e32 v7, s7, v8
1131 ; GFX9-NEXT: v_subrev_u32_e32 v7, s7, v7
1146 ; GFX10-NEXT: s_add_i32 s7, s13, s1
1150 ; GFX10-NEXT: s_xor_b32 s15, s7, s1
1162 ; GFX10-NEXT: s_sub_i32 s7, 0, s15
1179 ; GFX10-NEXT: v_mul_lo_u32 v5, s7, v1
1184 ; GFX10-NEXT: s_add_i32 s7, s9, s17
1192 ; GFX10-NEXT: s_xor_b32 s11, s7, s17
1293 ; GFX8-NEXT: s_addc_u32 s7, s13, s16
1295 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s7
1303 ; GFX8-NEXT: s_subb_u32 s13, 0, s7
1391 ; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s7, v4, v[1:2]
1392 ; GFX8-NEXT: v_mov_b32_e32 v5, s7
1396 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v6
1401 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v6
1407 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v9
1411 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v9
1511 ; GFX8-NEXT: v_mul_lo_u32 v7, s7, v2
1520 ; GFX8-NEXT: v_mul_lo_u32 v7, s7, v3
1521 ; GFX8-NEXT: v_mul_hi_u32 v2, s7, v2
1530 ; GFX8-NEXT: v_mul_hi_u32 v9, s7, v3
1536 ; GFX8-NEXT: v_mov_b32_e32 v10, s7
1541 ; GFX8-NEXT: v_sub_u32_e64 v6, s[0:1], s7, v6
1592 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
1606 ; GFX9-NEXT: s_addc_u32 s7, s13, s16
1608 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
1616 ; GFX9-NEXT: s_subb_u32 s13, 0, s7
1701 ; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[0:1], s7, v5, v[1:2]
1702 ; GFX9-NEXT: v_mov_b32_e32 v4, s7
1706 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v6
1711 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v6
1717 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v9
1721 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v9
1818 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v2
1821 ; GFX9-NEXT: v_mul_hi_u32 v2, s7, v2
1822 ; GFX9-NEXT: v_mul_hi_u32 v12, s7, v3
1827 ; GFX9-NEXT: v_mul_lo_u32 v9, s7, v3
1843 ; GFX9-NEXT: v_mov_b32_e32 v9, s7
1849 ; GFX9-NEXT: v_sub_u32_e32 v6, s7, v6
1908 ; GFX10-NEXT: s_mov_b32 s7, s6
1922 ; GFX10-NEXT: s_addc_u32 s7, s11, s12
1959 ; GFX10-NEXT: v_mad_u64_u32 v[1:2], s7, s3, v4, 0
1967 ; GFX10-NEXT: v_add_co_u32 v10, s7, v10, v12
1968 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s7
1969 ; GFX10-NEXT: v_add_co_u32 v0, s7, v13, v0
1971 ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s7
1973 ; GFX10-NEXT: v_add_co_u32 v10, s7, v10, v11
1976 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s7
1977 ; GFX10-NEXT: v_add_co_u32 v0, s7, v0, v14
1979 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s7
1981 ; GFX10-NEXT: v_add_co_u32 v8, s7, v8, v15
1982 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s7
1985 ; GFX10-NEXT: v_add_co_u32 v1, s7, v14, v1
1986 ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s7
1987 ; GFX10-NEXT: v_add_co_u32 v0, s7, v0, v10
1988 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s7
1989 ; GFX10-NEXT: v_add_co_u32 v8, s7, v8, v9
1990 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s7
1991 ; GFX10-NEXT: v_add_co_u32 v9, s7, v1, v16
1993 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7
1999 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s7, s20, v6, 0
2000 ; GFX10-NEXT: v_add_co_u32 v7, s7, v9, v8
2003 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s7
2012 ; GFX10-NEXT: v_mad_u64_u32 v[1:2], s7, s3, v4, 0
2211 ; GFX8-NEXT: s_ashr_i32 s7, s0, 31
2212 ; GFX8-NEXT: s_add_i32 s0, s0, s7
2213 ; GFX8-NEXT: s_xor_b32 s8, s0, s7
2226 ; GFX8-NEXT: s_xor_b32 s6, s5, s7
2262 ; GFX9-NEXT: s_xor_b32 s7, s1, s6
2263 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
2264 ; GFX9-NEXT: s_sub_i32 s1, 0, s7
2278 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s7
2281 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
2283 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
2286 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
2288 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
2309 ; GFX10-NEXT: s_xor_b32 s7, s1, s6
2311 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s7
2312 ; GFX10-NEXT: s_sub_i32 s1, 0, s7
2320 ; GFX10-NEXT: v_mul_lo_u32 v1, v0, s7
2325 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s7, v1
2326 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s7, v1
2330 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s7, v1
2331 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s7, v1
2435 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
2444 ; GFX9-NEXT: s_ashr_i32 s7, s0, 31
2445 ; GFX9-NEXT: s_add_i32 s0, s0, s7
2446 ; GFX9-NEXT: s_xor_b32 s8, s0, s7
2492 ; GFX9-NEXT: s_xor_b32 s6, s10, s7
2539 ; GFX10-NEXT: s_sub_i32 s7, 0, s2
2547 ; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1
2620 ; GFX8-NEXT: s_ashr_i32 s7, s0, 31
2621 ; GFX8-NEXT: s_add_i32 s0, s0, s7
2622 ; GFX8-NEXT: s_xor_b32 s8, s0, s7
2635 ; GFX8-NEXT: s_xor_b32 s6, s5, s7
2671 ; GFX9-NEXT: s_xor_b32 s7, s1, s6
2672 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
2673 ; GFX9-NEXT: s_sub_i32 s1, 0, s7
2687 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s7
2690 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
2692 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
2695 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
2697 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
2718 ; GFX10-NEXT: s_xor_b32 s7, s1, s6
2720 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s7
2721 ; GFX10-NEXT: s_sub_i32 s1, 0, s7
2729 ; GFX10-NEXT: v_mul_lo_u32 v1, v0, s7
2734 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s7, v1
2735 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s7, v1
2739 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s7, v1
2740 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s7, v1
2844 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
2852 ; GFX9-NEXT: s_sext_i32_i16 s0, s7
2858 ; GFX9-NEXT: s_bfe_i32 s5, s7, 0x100010
2859 ; GFX9-NEXT: s_ashr_i32 s7, s5, 31
2861 ; GFX9-NEXT: s_add_i32 s5, s5, s7
2862 ; GFX9-NEXT: s_xor_b32 s5, s5, s7
2913 ; GFX9-NEXT: s_xor_b32 s4, s11, s7
2945 ; GFX10-NEXT: s_sub_i32 s7, 0, s1
2953 ; GFX10-NEXT: v_mul_lo_u32 v3, s7, v1
3023 ; GFX8-NEXT: s_ashr_i32 s7, s0, 31
3024 ; GFX8-NEXT: s_add_i32 s0, s0, s7
3025 ; GFX8-NEXT: s_xor_b32 s8, s0, s7
3038 ; GFX8-NEXT: s_xor_b32 s6, s5, s7
3076 ; GFX9-NEXT: s_xor_b32 s7, s1, s6
3077 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
3078 ; GFX9-NEXT: s_sub_i32 s1, 0, s7
3092 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s7
3095 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
3097 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
3100 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
3102 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
3122 ; GFX10-NEXT: s_ashr_i32 s7, s0, 31
3124 ; GFX10-NEXT: s_add_i32 s0, s0, s7
3126 ; GFX10-NEXT: s_xor_b32 s0, s0, s7
3147 ; GFX10-NEXT: s_xor_b32 s4, s7, s6
3152 ; GFX10-NEXT: v_xor_b32_e32 v1, s7, v1
3154 ; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s7, v1
3173 ; GFX8-NEXT: s_bfe_i32 s0, s7, 0x1b0000
3174 ; GFX8-NEXT: s_ashr_i32 s7, s0, 31
3175 ; GFX8-NEXT: s_add_i32 s0, s0, s7
3176 ; GFX8-NEXT: s_xor_b32 s8, s0, s7
3189 ; GFX8-NEXT: s_xor_b32 s6, s5, s7
3227 ; GFX9-NEXT: s_xor_b32 s7, s1, s6
3228 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
3229 ; GFX9-NEXT: s_sub_i32 s1, 0, s7
3243 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, s7
3246 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
3248 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
3251 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
3253 ; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
3273 ; GFX10-NEXT: s_ashr_i32 s7, s0, 31
3275 ; GFX10-NEXT: s_add_i32 s0, s0, s7
3277 ; GFX10-NEXT: s_xor_b32 s0, s0, s7
3298 ; GFX10-NEXT: s_xor_b32 s4, s7, s6
3303 ; GFX10-NEXT: v_xor_b32_e32 v1, s7, v1
3305 ; GFX10-NEXT: v_subrev_nc_u32_e32 v1, s7, v1