Lines Matching refs:amount
8 define i8 @v_lshr_i8(i8 %value, i8 %amount) {
37 %result = lshr i8 %value, %amount
73 define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) {
85 %result = lshr i8 %value, %amount
104 define i24 @v_lshr_i24(i24 %value, i24 %amount) {
121 %result = lshr i24 %value, %amount
142 define amdgpu_ps i24 @s_lshr_i24(i24 inreg %value, i24 inreg %amount) {
154 %result = lshr i24 %value, %amount
172 define i32 @v_lshr_i32(i32 %value, i32 %amount) {
185 %result = lshr i32 %value, %amount
206 define amdgpu_ps i32 @s_lshr_i32(i32 inreg %value, i32 inreg %amount) {
216 %result = lshr i32 %value, %amount
234 define amdgpu_ps float @lshr_i32_sv(i32 inreg %value, i32 %amount) {
254 %result = lshr i32 %value, %amount
259 define amdgpu_ps float @lshr_i32_vs(i32 %value, i32 inreg %amount) {
269 %result = lshr i32 %value, %amount
274 define <2 x i32> @v_lshr_v2i32(<2 x i32> %value, <2 x i32> %amount) {
289 %result = lshr <2 x i32> %value, %amount
312 define amdgpu_ps <2 x i32> @s_lshr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) {
324 %result = lshr <2 x i32> %value, %amount
328 define <3 x i32> @v_lshr_v3i32(<3 x i32> %value, <3 x i32> %amount) {
345 %result = lshr <3 x i32> %value, %amount
349 define amdgpu_ps <3 x i32> @s_lshr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) {
363 %result = lshr <3 x i32> %value, %amount
367 define <4 x i32> @v_lshr_v4i32(<4 x i32> %value, <4 x i32> %amount) {
386 %result = lshr <4 x i32> %value, %amount
390 define amdgpu_ps <4 x i32> @s_lshr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) {
406 %result = lshr <4 x i32> %value, %amount
410 define <5 x i32> @v_lshr_v5i32(<5 x i32> %value, <5 x i32> %amount) {
431 %result = lshr <5 x i32> %value, %amount
435 define amdgpu_ps <5 x i32> @s_lshr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) {
453 %result = lshr <5 x i32> %value, %amount
457 define <16 x i32> @v_lshr_v16i32(<16 x i32> %value, <16 x i32> %amount) {
528 %result = lshr <16 x i32> %value, %amount
532 define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {
572 %result = lshr <16 x i32> %value, %amount
576 define i16 @v_lshr_i16(i16 %value, i16 %amount) {
603 %result = lshr i16 %value, %amount
622 define amdgpu_ps i16 @s_lshr_i16(i16 inreg %value, i16 inreg %amount) {
634 %result = lshr i16 %value, %amount
652 define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) {
674 %result = lshr i16 %value, %amount
679 define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) {
701 %result = lshr i16 %value, %amount
706 define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
738 %result = lshr <2 x i16> %value, %amount
775 define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {
817 %result = lshr <2 x i16> %value, %amount
822 define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
853 %result = lshr <2 x i16> %value, %amount
858 define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {
889 %result = lshr <2 x i16> %value, %amount
895 ; define <3 x i16> @v_lshr_v3i16(<3 x i16> %value, <3 x i16> %amount) {
896 ; %result = lshr <3 x i16> %value, %amount
900 ; define amdgpu_ps <3 x i16> @s_lshr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) {
901 ; %result = lshr <3 x i16> %value, %amount
905 define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) {
952 %result = lshr <4 x i16> %value, %amount
957 define amdgpu_ps <2 x i32> @s_lshr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) {
1025 %result = lshr <4 x i16> %value, %amount
1031 ; define <5 x i16> @v_lshr_v5i16(<5 x i16> %value, <5 x i16> %amount) {
1032 ; %result = lshr <5 x i16> %value, %amount
1036 ; define amdgpu_ps <5 x i16> @s_lshr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) {
1037 ; %result = lshr <5 x i16> %value, %amount
1041 ; define <3 x float> @v_lshr_v6i16(<6 x i16> %value, <6 x i16> %amount) {
1042 ; %result = lshr <6 x i16> %value, %amount
1047 ; define amdgpu_ps <3 x i32> @s_lshr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) {
1048 ; %result = lshr <6 x i16> %value, %amount
1053 define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
1126 %result = lshr <8 x i16> %value, %amount
1131 define amdgpu_ps <4 x i32> @s_lshr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) {
1251 %result = lshr <8 x i16> %value, %amount
1256 define i64 @v_lshr_i64(i64 %value, i64 %amount) {
1281 %result = lshr i64 %value, %amount
1378 define amdgpu_ps i64 @s_lshr_i64(i64 inreg %value, i64 inreg %amount) {
1388 %result = lshr i64 %value, %amount
1454 define amdgpu_ps <2 x float> @lshr_i64_sv(i64 inreg %value, i64 %amount) {
1474 %result = lshr i64 %value, %amount
1479 define amdgpu_ps <2 x float> @lshr_i64_vs(i64 %value, i64 inreg %amount) {
1499 %result = lshr i64 %value, %amount
1504 define <2 x i64> @v_lshr_v2i64(<2 x i64> %value, <2 x i64> %amount) {
1533 %result = lshr <2 x i64> %value, %amount
1570 define amdgpu_ps <2 x i64> @s_lshr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) {
1582 %result = lshr <2 x i64> %value, %amount
1586 define i65 @v_lshr_i65(i65 %value, i65 %amount) {
1697 %result = lshr i65 %value, %amount
1766 define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) {
1810 %result = lshr i65 %value, %amount
1839 ; define <2 x i65> @v_lshr_v2i65(<2 x i65> %value, <2 x i65> %amount) {
1840 ; %result = lshr <2 x i65> %value, %amount
1844 ; define amdgpu_ps <2 x i65> @s_lshr_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) {
1845 ; %result = lshr <2 x i65> %value, %amount