Lines Matching refs:IEEE

2 …ormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE %s
5 …rmal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
8 …rmal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
11 …0 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s
14 …0 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s
18 ; GFX6-IEEE-LABEL: v_fdiv_f32:
19 ; GFX6-IEEE:       ; %bb.0:
20 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
21 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
22 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
23 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
24 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
25 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
26 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
27 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
28 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
29 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
30 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
31 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
32 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
52 ; GFX89-IEEE-LABEL: v_fdiv_f32:
53 ; GFX89-IEEE:       ; %bb.0:
54 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
55 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
56 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
57 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
58 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
59 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
60 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v5, v3, v4
61 ; GFX89-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v3
62 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
63 ; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v3
64 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
65 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
66 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
86 ; GFX10-IEEE-LABEL: v_fdiv_f32:
87 ; GFX10-IEEE:       ; %bb.0:
88 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
89 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
90 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
91 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
92 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
93 ; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
94 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
95 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
96 ; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
97 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
98 ; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
99 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
100 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
101 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
122 ; GFX11-IEEE-LABEL: v_fdiv_f32:
123 ; GFX11-IEEE:       ; %bb.0:
124 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
125 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
126 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v1, v1, v0
127 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
128 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
129 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
130 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
131 ; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
132 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
133 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
134 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
135 ; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
136 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
137 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
138 ; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
139 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
140 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
141 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
142 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
200 ; GFX6-IEEE-LABEL: v_fdiv_f32_ulp25:
201 ; GFX6-IEEE:       ; %bb.0:
202 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
203 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
204 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
205 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
206 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
207 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
208 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
209 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
210 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
211 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
212 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
213 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
214 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
229 ; GFX89-IEEE-LABEL: v_fdiv_f32_ulp25:
230 ; GFX89-IEEE:       ; %bb.0:
231 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
232 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
233 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
234 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
235 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
236 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
237 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v5, v3, v4
238 ; GFX89-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v3
239 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
240 ; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v3
241 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
242 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
243 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
245 ; GFX10-IEEE-LABEL: v_fdiv_f32_ulp25:
246 ; GFX10-IEEE:       ; %bb.0:
247 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
248 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
249 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
250 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
251 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
252 ; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
253 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
254 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
255 ; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
256 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
257 ; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
258 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
259 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
260 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
274 ; GFX11-IEEE-LABEL: v_fdiv_f32_ulp25:
275 ; GFX11-IEEE:       ; %bb.0:
276 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
277 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
278 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v1, v1, v0
279 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
280 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
281 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
282 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
283 ; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
284 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
285 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
286 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
287 ; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
288 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
289 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
290 ; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
291 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
292 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
293 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
294 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
315 ; GFX6-IEEE-LABEL: v_rcp_f32:
316 ; GFX6-IEEE:       ; %bb.0:
317 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
318 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
319 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
320 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
321 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
322 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, v4, v2, v2
323 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v4, v3, v2
324 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v3
325 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v2, v4
326 ; GFX6-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v3
327 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
328 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
329 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
349 ; GFX89-IEEE-LABEL: v_rcp_f32:
350 ; GFX89-IEEE:       ; %bb.0:
351 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
352 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
353 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
354 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v3, v1
355 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
356 ; GFX89-IEEE-NEXT:    v_fma_f32 v3, v4, v3, v3
357 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v4, v2, v3
358 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v2
359 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v3, v4
360 ; GFX89-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v2
361 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
362 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
363 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
383 ; GFX10-IEEE-LABEL: v_rcp_f32:
384 ; GFX10-IEEE:       ; %bb.0:
385 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
386 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
387 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
388 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
389 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
390 ; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
391 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
392 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
393 ; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
394 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
395 ; GFX10-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
396 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
397 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
398 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
419 ; GFX11-IEEE-LABEL: v_rcp_f32:
420 ; GFX11-IEEE:       ; %bb.0:
421 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
422 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
423 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v1, null, v0, v0, 1.0
424 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
425 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
426 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
427 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
428 ; GFX11-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
429 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
430 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
431 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
432 ; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
433 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
434 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
435 ; GFX11-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
436 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
437 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
438 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
439 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
469 ; GFX6-IEEE-LABEL: v_rcp_f32_arcp:
470 ; GFX6-IEEE:       ; %bb.0:
471 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
472 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
473 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
474 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
475 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
476 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, v4, v2, v2
477 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v4, v3, v2
478 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v3
479 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v2, v4
480 ; GFX6-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v3
481 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
482 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
483 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
503 ; GFX89-IEEE-LABEL: v_rcp_f32_arcp:
504 ; GFX89-IEEE:       ; %bb.0:
505 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
506 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
507 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
508 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v3, v1
509 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
510 ; GFX89-IEEE-NEXT:    v_fma_f32 v3, v4, v3, v3
511 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v4, v2, v3
512 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v2
513 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v3, v4
514 ; GFX89-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v2
515 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
516 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
517 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
537 ; GFX10-IEEE-LABEL: v_rcp_f32_arcp:
538 ; GFX10-IEEE:       ; %bb.0:
539 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
540 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
541 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
542 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
543 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
544 ; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
545 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
546 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
547 ; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
548 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
549 ; GFX10-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
550 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
551 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
552 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
573 ; GFX11-IEEE-LABEL: v_rcp_f32_arcp:
574 ; GFX11-IEEE:       ; %bb.0:
575 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
576 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
577 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v1, null, v0, v0, 1.0
578 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
579 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
580 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
581 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
582 ; GFX11-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
583 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
584 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
585 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
586 ; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
587 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
588 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
589 ; GFX11-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
590 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
591 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
592 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
593 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
647 ; GCN-IEEE-LABEL: v_rcp_f32_ulp25:
648 ; GCN-IEEE:       ; %bb.0:
649 ; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
650 ; GCN-IEEE-NEXT:    v_mov_b32_e32 v1, 0x6f800000
651 ; GCN-IEEE-NEXT:    v_mov_b32_e32 v2, 0x2f800000
652 ; GCN-IEEE-NEXT:    v_cmp_gt_f32_e64 vcc, |v0|, v1
653 ; GCN-IEEE-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
654 ; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v1
655 ; GCN-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
656 ; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
657 ; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v1, v0
658 ; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
666 ; GFX10-IEEE-LABEL: v_rcp_f32_ulp25:
667 ; GFX10-IEEE:       ; %bb.0:
668 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
669 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
670 ; GFX10-IEEE-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v0|
671 ; GFX10-IEEE-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s4
672 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v1
673 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
674 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
675 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v1, v0
676 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
685 ; GFX11-IEEE-LABEL: v_rcp_f32_ulp25:
686 ; GFX11-IEEE:       ; %bb.0:
687 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
688 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
689 ; GFX11-IEEE-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v0|
690 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
691 ; GFX11-IEEE-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s0
692 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v1
693 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
694 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
695 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
696 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
697 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v0, v1, v0
698 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
739 ; GFX6-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
740 ; GFX6-IEEE:       ; %bb.0:
741 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
742 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
743 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
744 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
745 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
746 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
747 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
748 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
749 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
750 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
751 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
752 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
753 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
768 ; GFX89-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
769 ; GFX89-IEEE:       ; %bb.0:
770 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
771 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
772 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
773 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
774 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
775 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
776 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v5, v3, v4
777 ; GFX89-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v3
778 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
779 ; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v3
780 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
781 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
782 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
784 ; GFX10-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
785 ; GFX10-IEEE:       ; %bb.0:
786 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
787 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
788 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
789 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
790 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
791 ; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
792 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
793 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
794 ; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
795 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
796 ; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
797 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
798 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
799 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
813 ; GFX11-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
814 ; GFX11-IEEE:       ; %bb.0:
815 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
816 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
817 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v1, v1, v0
818 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
819 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
820 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
821 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
822 ; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
823 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
824 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
825 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
826 ; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
827 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
828 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
829 ; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
830 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
831 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
832 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
833 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
854 ; GFX6-IEEE-LABEL: v_fdiv_v2f32:
855 ; GFX6-IEEE:       ; %bb.0:
856 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
857 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
858 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
859 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
860 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
861 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
862 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
863 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
864 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
865 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
866 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
867 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
868 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
869 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
870 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
871 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
872 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
873 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
874 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
875 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
876 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
877 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
878 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
879 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
912 ; GFX89-IEEE-LABEL: v_fdiv_v2f32:
913 ; GFX89-IEEE:       ; %bb.0:
914 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
915 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
916 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
917 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
918 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v3, v1
919 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v8, v4
920 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v9, v5
921 ; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v4, v8, 1.0
922 ; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v8, v8
923 ; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v5, v9, 1.0
924 ; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v9, v9
925 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v10, v6, v8
926 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v11, v7, v9
927 ; GFX89-IEEE-NEXT:    v_fma_f32 v12, -v4, v10, v6
928 ; GFX89-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v7
929 ; GFX89-IEEE-NEXT:    v_fma_f32 v10, v12, v8, v10
930 ; GFX89-IEEE-NEXT:    v_fma_f32 v11, v13, v9, v11
931 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v4, v10, v6
932 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v7
933 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v8, v10
934 ; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
935 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v9, v11
936 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
937 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
938 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
971 ; GFX10-IEEE-LABEL: v_fdiv_v2f32:
972 ; GFX10-IEEE:       ; %bb.0:
973 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
974 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
975 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
976 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, s4, v3, v3, v1
977 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
978 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
979 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
980 ; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
981 ; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
982 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
983 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
984 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
985 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
986 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
987 ; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
988 ; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
989 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
990 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
991 ; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
992 ; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
993 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
994 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
995 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
996 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
997 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
998 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1032 ; GFX11-IEEE-LABEL: v_fdiv_v2f32:
1033 ; GFX11-IEEE:       ; %bb.0:
1034 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1035 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1036 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, null, v2, v2, v0
1037 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, null, v3, v3, v1
1038 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
1039 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
1040 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
1041 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
1042 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1043 ; GFX11-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
1044 ; GFX11-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
1045 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1046 ; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
1047 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, s0, v1, v3, v1
1048 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
1049 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1050 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
1051 ; GFX11-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
1052 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1053 ; GFX11-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
1054 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
1055 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1056 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
1057 ; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
1058 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1059 ; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
1060 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
1061 ; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
1062 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1063 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
1064 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1065 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
1066 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1067 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1148 ; GFX6-IEEE-LABEL: v_fdiv_v2f32_ulp25:
1149 ; GFX6-IEEE:       ; %bb.0:
1150 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1151 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1152 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
1153 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
1154 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1155 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
1156 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
1157 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
1158 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
1159 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
1160 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
1161 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1162 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
1163 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1164 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
1165 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
1166 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
1167 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
1168 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
1169 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
1170 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
1171 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
1172 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
1173 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1194 ; GFX89-IEEE-LABEL: v_fdiv_v2f32_ulp25:
1195 ; GFX89-IEEE:       ; %bb.0:
1196 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1197 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1198 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1199 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
1200 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v3, v1
1201 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v8, v4
1202 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v9, v5
1203 ; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v4, v8, 1.0
1204 ; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v8, v8
1205 ; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v5, v9, 1.0
1206 ; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v9, v9
1207 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v10, v6, v8
1208 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v11, v7, v9
1209 ; GFX89-IEEE-NEXT:    v_fma_f32 v12, -v4, v10, v6
1210 ; GFX89-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v7
1211 ; GFX89-IEEE-NEXT:    v_fma_f32 v10, v12, v8, v10
1212 ; GFX89-IEEE-NEXT:    v_fma_f32 v11, v13, v9, v11
1213 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v4, v10, v6
1214 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v7
1215 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v8, v10
1216 ; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
1217 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v9, v11
1218 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1219 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1220 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
1222 ; GFX10-IEEE-LABEL: v_fdiv_v2f32_ulp25:
1223 ; GFX10-IEEE:       ; %bb.0:
1224 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1225 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1226 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
1227 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, s4, v3, v3, v1
1228 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
1229 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
1230 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
1231 ; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
1232 ; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
1233 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
1234 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
1235 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
1236 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
1237 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
1238 ; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
1239 ; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
1240 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
1241 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
1242 ; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
1243 ; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
1244 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
1245 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
1246 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
1247 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1248 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1249 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1269 ; GFX11-IEEE-LABEL: v_fdiv_v2f32_ulp25:
1270 ; GFX11-IEEE:       ; %bb.0:
1271 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1272 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1273 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, null, v2, v2, v0
1274 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, null, v3, v3, v1
1275 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
1276 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
1277 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
1278 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
1279 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1280 ; GFX11-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
1281 ; GFX11-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
1282 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1283 ; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
1284 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, s0, v1, v3, v1
1285 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
1286 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1287 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
1288 ; GFX11-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
1289 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1290 ; GFX11-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
1291 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
1292 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1293 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
1294 ; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
1295 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1296 ; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
1297 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
1298 ; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
1299 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1300 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
1301 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1302 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
1303 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1304 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1329 ; GFX6-IEEE-LABEL: v_rcp_v2f32:
1330 ; GFX6-IEEE:       ; %bb.0:
1331 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1332 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1333 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
1334 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1335 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1336 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
1337 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
1338 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
1339 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
1340 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
1341 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1342 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1343 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
1344 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1345 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
1346 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
1347 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
1348 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
1349 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
1350 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
1351 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
1352 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1353 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1354 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1387 ; GFX89-IEEE-LABEL: v_rcp_v2f32:
1388 ; GFX89-IEEE:       ; %bb.0:
1389 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1390 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1391 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1392 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1393 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
1394 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v6, v2
1395 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v7, v3
1396 ; GFX89-IEEE-NEXT:    v_fma_f32 v8, -v2, v6, 1.0
1397 ; GFX89-IEEE-NEXT:    v_fma_f32 v6, v8, v6, v6
1398 ; GFX89-IEEE-NEXT:    v_fma_f32 v9, -v3, v7, 1.0
1399 ; GFX89-IEEE-NEXT:    v_fma_f32 v7, v9, v7, v7
1400 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v8, v4, v6
1401 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v9, v5, v7
1402 ; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v2, v8, v4
1403 ; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v5
1404 ; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v6, v8
1405 ; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v7, v9
1406 ; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v8, v4
1407 ; GFX89-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v5
1408 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v6, v8
1409 ; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
1410 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v7, v9
1411 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1412 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1413 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
1446 ; GFX10-IEEE-LABEL: v_rcp_v2f32:
1447 ; GFX10-IEEE:       ; %bb.0:
1448 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1449 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1450 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1451 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v3, s4, v1, v1, 1.0
1452 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1453 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1454 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1455 ; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1456 ; GFX10-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1457 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v4
1458 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v6, s4, 1.0, v1, 1.0
1459 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v5, v7, v5
1460 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1461 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1462 ; GFX10-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1463 ; GFX10-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1464 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1465 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1466 ; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1467 ; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1468 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1469 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
1470 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1471 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1472 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1473 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1507 ; GFX11-IEEE-LABEL: v_rcp_v2f32:
1508 ; GFX11-IEEE:       ; %bb.0:
1509 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1510 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1511 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v0, v0, 1.0
1512 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v3, null, v1, v1, 1.0
1513 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1514 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
1515 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1516 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1517 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1518 ; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1519 ; GFX11-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1520 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1521 ; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v5
1522 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v6, s0, 1.0, v1, 1.0
1523 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1524 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1525 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1526 ; GFX11-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1527 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1528 ; GFX11-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1529 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1530 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1531 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1532 ; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1533 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1534 ; GFX11-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1535 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1536 ; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
1537 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1538 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1539 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1540 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
1541 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1542 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1590 ; GFX6-IEEE-LABEL: v_rcp_v2f32_arcp:
1591 ; GFX6-IEEE:       ; %bb.0:
1592 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1593 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1594 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
1595 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1596 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1597 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
1598 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
1599 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
1600 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
1601 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
1602 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1603 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1604 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
1605 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1606 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
1607 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
1608 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
1609 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
1610 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
1611 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
1612 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
1613 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1614 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1615 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1648 ; GFX89-IEEE-LABEL: v_rcp_v2f32_arcp:
1649 ; GFX89-IEEE:       ; %bb.0:
1650 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1651 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1652 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1653 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1654 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
1655 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v6, v2
1656 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v7, v3
1657 ; GFX89-IEEE-NEXT:    v_fma_f32 v8, -v2, v6, 1.0
1658 ; GFX89-IEEE-NEXT:    v_fma_f32 v6, v8, v6, v6
1659 ; GFX89-IEEE-NEXT:    v_fma_f32 v9, -v3, v7, 1.0
1660 ; GFX89-IEEE-NEXT:    v_fma_f32 v7, v9, v7, v7
1661 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v8, v4, v6
1662 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v9, v5, v7
1663 ; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v2, v8, v4
1664 ; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v5
1665 ; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v6, v8
1666 ; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v7, v9
1667 ; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v8, v4
1668 ; GFX89-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v5
1669 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v6, v8
1670 ; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
1671 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v7, v9
1672 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1673 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1674 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
1707 ; GFX10-IEEE-LABEL: v_rcp_v2f32_arcp:
1708 ; GFX10-IEEE:       ; %bb.0:
1709 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1710 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1711 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1712 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v3, s4, v1, v1, 1.0
1713 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1714 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1715 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1716 ; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1717 ; GFX10-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1718 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v4
1719 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v6, s4, 1.0, v1, 1.0
1720 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v5, v7, v5
1721 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1722 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1723 ; GFX10-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1724 ; GFX10-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1725 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1726 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1727 ; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1728 ; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1729 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1730 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
1731 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1732 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1733 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1734 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1768 ; GFX11-IEEE-LABEL: v_rcp_v2f32_arcp:
1769 ; GFX11-IEEE:       ; %bb.0:
1770 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1771 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1772 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v0, v0, 1.0
1773 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v3, null, v1, v1, 1.0
1774 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1775 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
1776 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1777 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1778 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1779 ; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1780 ; GFX11-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1781 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1782 ; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v5
1783 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v6, s0, 1.0, v1, 1.0
1784 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1785 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1786 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1787 ; GFX11-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1788 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1789 ; GFX11-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1790 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1791 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1792 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1793 ; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1794 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1795 ; GFX11-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1796 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1797 ; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
1798 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1799 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1800 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1801 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
1802 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1803 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1878 ; GCN-IEEE-LABEL: v_rcp_v2f32_ulp25:
1879 ; GCN-IEEE:       ; %bb.0:
1880 ; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1881 ; GCN-IEEE-NEXT:    s_mov_b32 s4, 0x6f800000
1882 ; GCN-IEEE-NEXT:    v_mov_b32_e32 v2, 0x2f800000
1883 ; GCN-IEEE-NEXT:    v_cmp_gt_f32_e64 vcc, |v0|, s4
1884 ; GCN-IEEE-NEXT:    v_cndmask_b32_e32 v3, 1.0, v2, vcc
1885 ; GCN-IEEE-NEXT:    v_cmp_gt_f32_e64 vcc, |v1|, s4
1886 ; GCN-IEEE-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
1887 ; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v3
1888 ; GCN-IEEE-NEXT:    v_mul_f32_e32 v1, v1, v2
1889 ; GCN-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
1890 ; GCN-IEEE-NEXT:    v_rcp_f32_e32 v1, v1
1891 ; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
1892 ; GCN-IEEE-NEXT:    v_mul_f32_e32 v1, 1.0, v1
1893 ; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v3, v0
1894 ; GCN-IEEE-NEXT:    v_mul_f32_e32 v1, v2, v1
1895 ; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
1904 ; GFX10-IEEE-LABEL: v_rcp_v2f32_ulp25:
1905 ; GFX10-IEEE:       ; %bb.0:
1906 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1907 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1908 ; GFX10-IEEE-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v0|
1909 ; GFX10-IEEE-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
1910 ; GFX10-IEEE-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
1911 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v2
1912 ; GFX10-IEEE-NEXT:    v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s4
1913 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
1914 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v1, v1, v3
1915 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v1, v1
1916 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
1917 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v2, v0
1918 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v1, 1.0, v1
1919 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v1, v3, v1
1920 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1930 ; GFX11-IEEE-LABEL: v_rcp_v2f32_ulp25:
1931 ; GFX11-IEEE:       ; %bb.0:
1932 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1933 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1934 ; GFX11-IEEE-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v0|
1935 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
1936 ; GFX11-IEEE-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
1937 ; GFX11-IEEE-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
1938 ; GFX11-IEEE-NEXT:    v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s0
1939 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1940 ; GFX11-IEEE-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
1941 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
1942 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
1943 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v1, v1
1944 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1945 ; GFX11-IEEE-NEXT:    v_dual_mul_f32 v0, 1.0, v0 :: v_dual_mul_f32 v1, 1.0, v1
1946 ; GFX11-IEEE-NEXT:    v_dual_mul_f32 v0, v2, v0 :: v_dual_mul_f32 v1, v3, v1
1947 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1994 ; GFX6-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
1995 ; GFX6-IEEE:       ; %bb.0:
1996 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1997 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1998 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
1999 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
2000 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
2001 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
2002 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
2003 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
2004 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
2005 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
2006 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
2007 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
2008 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
2009 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
2010 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
2011 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
2012 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
2013 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
2014 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
2015 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
2016 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
2017 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
2018 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
2019 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
2040 ; GFX89-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
2041 ; GFX89-IEEE:       ; %bb.0:
2042 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2043 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
2044 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
2045 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
2046 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v3, v1
2047 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v8, v4
2048 ; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v9, v5
2049 ; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v4, v8, 1.0
2050 ; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v8, v8
2051 ; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v5, v9, 1.0
2052 ; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v9, v9
2053 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v10, v6, v8
2054 ; GFX89-IEEE-NEXT:    v_mul_f32_e32 v11, v7, v9
2055 ; GFX89-IEEE-NEXT:    v_fma_f32 v12, -v4, v10, v6
2056 ; GFX89-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v7
2057 ; GFX89-IEEE-NEXT:    v_fma_f32 v10, v12, v8, v10
2058 ; GFX89-IEEE-NEXT:    v_fma_f32 v11, v13, v9, v11
2059 ; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v4, v10, v6
2060 ; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v7
2061 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v8, v10
2062 ; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
2063 ; GFX89-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v9, v11
2064 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
2065 ; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
2066 ; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
2068 ; GFX10-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
2069 ; GFX10-IEEE:       ; %bb.0:
2070 ; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2071 ; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
2072 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
2073 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, s4, v3, v3, v1
2074 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
2075 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
2076 ; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
2077 ; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
2078 ; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
2079 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
2080 ; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
2081 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
2082 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
2083 ; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
2084 ; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
2085 ; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
2086 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
2087 ; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
2088 ; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
2089 ; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
2090 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
2091 ; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
2092 ; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
2093 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
2094 ; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
2095 ; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
2115 ; GFX11-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
2116 ; GFX11-IEEE:       ; %bb.0:
2117 ; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2118 ; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
2119 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, null, v2, v2, v0
2120 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, null, v3, v3, v1
2121 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
2122 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
2123 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
2124 ; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
2125 ; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
2126 ; GFX11-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
2127 ; GFX11-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
2128 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
2129 ; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
2130 ; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, s0, v1, v3, v1
2131 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
2132 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2133 ; GFX11-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
2134 ; GFX11-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
2135 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2136 ; GFX11-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
2137 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
2138 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2139 ; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
2140 ; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
2141 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2142 ; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
2143 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
2144 ; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
2145 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2146 ; GFX11-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
2147 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
2148 ; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
2149 ; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
2150 ; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]