Lines Matching refs:IEEE

3 …iti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6,GFX6-IEEE %s
19 ; GFX6-IEEE-LABEL: v_fdiv_f16:
20 ; GFX6-IEEE:       ; %bb.0:
21 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
22 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
23 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
24 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
25 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
26 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
27 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
28 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
29 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
30 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
31 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
32 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
33 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
34 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
35 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
36 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
138 ; GFX6-IEEE-LABEL: v_fdiv_f16_ulp25:
139 ; GFX6-IEEE:       ; %bb.0:
140 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
141 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
142 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
143 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
144 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
145 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
146 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
147 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
148 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
149 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
150 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
151 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
152 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
153 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
154 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
155 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
219 ; GFX6-IEEE-LABEL: v_rcp_f16:
220 ; GFX6-IEEE:       ; %bb.0:
221 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
222 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, 1.0
223 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
224 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v1
225 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
226 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v1, v0, v1
227 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
228 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
229 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
230 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
231 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
232 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
233 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
234 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, v1
235 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
236 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
300 ; GFX6-IEEE-LABEL: v_rcp_f16_arcp:
301 ; GFX6-IEEE:       ; %bb.0:
302 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
303 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, 1.0
304 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
305 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v1
306 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
307 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v1, v0, v1
308 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
309 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
310 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
311 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
312 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
313 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
314 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
315 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, v1
316 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
317 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
408 ; GFX6-IEEE-LABEL: v_rcp_f16_ulp25:
409 ; GFX6-IEEE:       ; %bb.0:
410 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
411 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, 1.0
412 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
413 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v1
414 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
415 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v1, v0, v1
416 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
417 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
418 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
419 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
420 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
421 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
422 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
423 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, v1
424 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
425 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
504 ; GFX6-IEEE-LABEL: v_fdiv_f16_arcp_ulp25:
505 ; GFX6-IEEE:       ; %bb.0:
506 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
507 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
508 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
509 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
510 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
511 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
512 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
513 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
514 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
515 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
516 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
517 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
518 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
519 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
520 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
521 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
585 ; GFX6-IEEE-LABEL: v_fdiv_v2f16:
586 ; GFX6-IEEE:       ; %bb.0:
587 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
588 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
589 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v2
590 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
591 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v3
592 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
593 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
594 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
595 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
596 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
597 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
598 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
599 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
600 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
601 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
602 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
603 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v3, v3, v1
604 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
605 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1
606 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
607 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
608 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
609 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
610 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v6, v5
611 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
612 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v6, v5
613 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
614 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
615 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
616 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
816 ; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25:
817 ; GFX6-IEEE:       ; %bb.0:
818 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
819 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
820 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v2
821 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
822 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v3
823 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
824 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
825 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
826 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
827 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
828 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
829 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
830 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
831 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
832 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
833 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
834 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v3, v3, v1
835 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
836 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1
837 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
838 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
839 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
840 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
841 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v6, v5
842 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
843 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v6, v5
844 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
845 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
846 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
847 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
979 ; GFX6-IEEE-LABEL: v_rcp_v2f16:
980 ; GFX6-IEEE:       ; %bb.0:
981 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
982 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, 1.0
983 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
984 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
985 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v2
986 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
987 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v2
988 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
989 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
990 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
991 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
992 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
993 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
994 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
995 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v2
996 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v2
997 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
998 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v1, v2
999 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
1000 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
1001 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
1002 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
1003 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
1004 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
1005 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
1006 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
1007 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, v2
1008 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
1009 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1134 ; GFX6-IEEE-LABEL: v_rcp_v2f16_arcp:
1135 ; GFX6-IEEE:       ; %bb.0:
1136 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1137 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, 1.0
1138 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
1139 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
1140 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v2
1141 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
1142 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v2
1143 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
1144 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
1145 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
1146 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
1147 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
1148 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
1149 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
1150 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v2
1151 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v2
1152 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
1153 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v1, v2
1154 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
1155 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
1156 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
1157 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
1158 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
1159 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
1160 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
1161 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
1162 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, v2
1163 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
1164 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1347 ; GFX6-IEEE-LABEL: v_rcp_v2f16_ulp25:
1348 ; GFX6-IEEE:       ; %bb.0:
1349 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1350 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, 1.0
1351 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
1352 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
1353 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v2
1354 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
1355 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v2
1356 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
1357 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
1358 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
1359 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
1360 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
1361 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
1362 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
1363 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v2
1364 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v2
1365 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
1366 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v2, v1, v2
1367 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
1368 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
1369 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
1370 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
1371 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
1372 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
1373 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
1374 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
1375 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, v2
1376 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
1377 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1529 ; GFX6-IEEE-LABEL: v_fdiv_v2f16_arcp_ulp25:
1530 ; GFX6-IEEE:       ; %bb.0:
1531 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1532 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
1533 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v2
1534 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
1535 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v3
1536 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1537 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
1538 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
1539 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1540 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
1541 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
1542 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
1543 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
1544 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
1545 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
1546 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1547 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v3, v3, v1
1548 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1549 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1
1550 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
1551 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1552 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
1553 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
1554 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v2, v6, v5
1555 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
1556 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v6, v5
1557 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
1558 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
1559 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v1
1560 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]