Lines Matching refs:amount
8 define i8 @v_ashr_i8(i8 %value, i8 %amount) {
38 %result = ashr i8 %value, %amount
75 define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) {
102 %result = ashr i8 %value, %amount
123 define i24 @v_ashr_i24(i24 %value, i24 %amount) {
140 %result = ashr i24 %value, %amount
163 define amdgpu_ps i24 @s_ashr_i24(i24 inreg %value, i24 inreg %amount) {
175 %result = ashr i24 %value, %amount
195 define i32 @v_ashr_i32(i32 %value, i32 %amount) {
208 %result = ashr i32 %value, %amount
229 define amdgpu_ps i32 @s_ashr_i32(i32 inreg %value, i32 inreg %amount) {
239 %result = ashr i32 %value, %amount
257 define amdgpu_ps float @ashr_i32_sv(i32 inreg %value, i32 %amount) {
277 %result = ashr i32 %value, %amount
282 define amdgpu_ps float @ashr_i32_vs(i32 %value, i32 inreg %amount) {
292 %result = ashr i32 %value, %amount
297 define <2 x i32> @v_ashr_v2i32(<2 x i32> %value, <2 x i32> %amount) {
312 %result = ashr <2 x i32> %value, %amount
335 define amdgpu_ps <2 x i32> @s_ashr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) {
347 %result = ashr <2 x i32> %value, %amount
351 define <3 x i32> @v_ashr_v3i32(<3 x i32> %value, <3 x i32> %amount) {
368 %result = ashr <3 x i32> %value, %amount
372 define amdgpu_ps <3 x i32> @s_ashr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) {
386 %result = ashr <3 x i32> %value, %amount
390 define <4 x i32> @v_ashr_v4i32(<4 x i32> %value, <4 x i32> %amount) {
409 %result = ashr <4 x i32> %value, %amount
413 define amdgpu_ps <4 x i32> @s_ashr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) {
429 %result = ashr <4 x i32> %value, %amount
433 define <5 x i32> @v_ashr_v5i32(<5 x i32> %value, <5 x i32> %amount) {
454 %result = ashr <5 x i32> %value, %amount
458 define amdgpu_ps <5 x i32> @s_ashr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) {
476 %result = ashr <5 x i32> %value, %amount
480 define <16 x i32> @v_ashr_v16i32(<16 x i32> %value, <16 x i32> %amount) {
551 %result = ashr <16 x i32> %value, %amount
555 define amdgpu_ps <16 x i32> @s_ashr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {
595 %result = ashr <16 x i32> %value, %amount
599 define i16 @v_ashr_i16(i16 %value, i16 %amount) {
626 %result = ashr i16 %value, %amount
645 define amdgpu_ps i16 @s_ashr_i16(i16 inreg %value, i16 inreg %amount) {
672 %result = ashr i16 %value, %amount
692 define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) {
714 %result = ashr i16 %value, %amount
719 define amdgpu_ps half @ashr_i16_vs(i16 %value, i16 inreg %amount) {
741 %result = ashr i16 %value, %amount
746 define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
778 %result = ashr <2 x i16> %value, %amount
817 define amdgpu_ps i32 @s_ashr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {
864 %result = ashr <2 x i16> %value, %amount
869 define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
902 %result = ashr <2 x i16> %value, %amount
907 define amdgpu_ps float @ashr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {
940 %result = ashr <2 x i16> %value, %amount
946 ; define <3 x i16> @v_ashr_v3i16(<3 x i16> %value, <3 x i16> %amount) {
947 ; %result = ashr <3 x i16> %value, %amount
951 ; define amdgpu_ps <3 x i16> @s_ashr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) {
952 ; %result = ashr <3 x i16> %value, %amount
956 define <2 x float> @v_ashr_v4i16(<4 x i16> %value, <4 x i16> %amount) {
1007 %result = ashr <4 x i16> %value, %amount
1012 define amdgpu_ps <2 x i32> @s_ashr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) {
1090 %result = ashr <4 x i16> %value, %amount
1096 ; define <5 x i16> @v_ashr_v5i16(<5 x i16> %value, <5 x i16> %amount) {
1097 ; %result = ashr <5 x i16> %value, %amount
1101 ; define amdgpu_ps <5 x i16> @s_ashr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) {
1102 ; %result = ashr <5 x i16> %value, %amount
1106 ; define <3 x float> @v_ashr_v6i16(<6 x i16> %value, <6 x i16> %amount) {
1107 ; %result = ashr <6 x i16> %value, %amount
1112 ; define amdgpu_ps <3 x i32> @s_ashr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) {
1113 ; %result = ashr <6 x i16> %value, %amount
1118 define <4 x float> @v_ashr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
1199 %result = ashr <8 x i16> %value, %amount
1204 define amdgpu_ps <4 x i32> @s_ashr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) {
1344 %result = ashr <8 x i16> %value, %amount
1349 define i64 @v_ashr_i64(i64 %value, i64 %amount) {
1374 %result = ashr i64 %value, %amount
1465 define amdgpu_ps i64 @s_ashr_i64(i64 inreg %value, i64 inreg %amount) {
1475 %result = ashr i64 %value, %amount
1542 define amdgpu_ps <2 x float> @ashr_i64_sv(i64 inreg %value, i64 %amount) {
1562 %result = ashr i64 %value, %amount
1567 define amdgpu_ps <2 x float> @ashr_i64_vs(i64 %value, i64 inreg %amount) {
1587 %result = ashr i64 %value, %amount
1592 define <2 x i64> @v_ashr_v2i64(<2 x i64> %value, <2 x i64> %amount) {
1621 %result = ashr <2 x i64> %value, %amount
1658 define amdgpu_ps <2 x i64> @s_ashr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) {
1670 %result = ashr <2 x i64> %value, %amount
1674 define i65 @v_ashr_i65(i65 %value, i65 %amount) {
1791 %result = ashr i65 %value, %amount
1848 define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
1896 %result = ashr i65 %value, %amount
1925 ; define <2 x i65> @v_ashr_v2i65(<2 x i65> %value, <2 x i65> %amount) {
1926 ; %result = ashr <2 x i65> %value, %amount
1930 ; define amdgpu_ps <2 x i65> @s_ashr_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) {
1931 ; %result = ashr <2 x i65> %value, %amount