Lines Matching refs:ADDR

7 ; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
9 ; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x[[ADDR]]]
12 ; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
48 ; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
50 ; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x[[ADDR]]]
53 ; CHECK-NEXT: stlxr  [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
67 ; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
69 ; CHECK-NEXT: ldxr   [[RESULT:x[0-9]+]], [x[[ADDR]]]
72 ; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
99 ; CHECK: mov    x[[ADDR:[0-9]+]], x0
101 ; CHECK: ldaxr   x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
104 ; CHECK: stlxr   [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
129 ; CHECK: mov    x[[ADDR:[0-9]+]], x0
131 ; CHECK: ldxr   [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
133 ; CHECK: stxr   [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
186 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
187 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
211 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
212 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
236 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
237 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
261 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
262 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
291 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
292 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
313 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
314 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
335 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
336 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
358 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
359 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]