Lines Matching refs:imul
111 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>,
115 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
119 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>,
123 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>,
130 "imul{b}\t$src", []>, SchedLoadReg<WriteIMul8>;
134 "imul{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIMul16>;
138 "imul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMul32>;
142 "imul{q}\t$src", []>, SchedLoadReg<WriteIMul64>,
155 "imul{w}\t{$src2, $dst|$dst, $src2}",
160 "imul{l}\t{$src2, $dst|$dst, $src2}",
166 "imul{q}\t{$src2, $dst|$dst, $src2}",
175 "imul{w}\t{$src2, $dst|$dst, $src2}",
181 "imul{l}\t{$src2, $dst|$dst, $src2}",
187 "imul{q}\t{$src2, $dst|$dst, $src2}",
203 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
209 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
215 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
227 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
241 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
248 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
254 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
274 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",