Lines Matching refs:OpSize16
20 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize16;
70 []>, OpSize16, Sched<[WriteIMul16]>;
96 "mul{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIMul16>;
116 OpSize16, Sched<[WriteIMul16]>;
134 "imul{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIMul16>;
158 Sched<[WriteIMul16Reg]>, TB, OpSize16;
178 Sched<[WriteIMul16Reg.Folded, WriteIMul16Reg.ReadAfterFold]>, TB, OpSize16;
206 Sched<[WriteIMul16Imm]>, OpSize16;
212 Sched<[WriteIMul16Imm]>, OpSize16;
245 Sched<[WriteIMul16Imm.Folded]>, OpSize16;
251 Sched<[WriteIMul16Imm.Folded]>, OpSize16;
288 "div{w}\t$src", []>, Sched<[WriteDiv16]>, OpSize16;
303 "div{w}\t$src", []>, OpSize16, SchedLoadReg<WriteDiv16>;
320 "idiv{w}\t$src", []>, Sched<[WriteIDiv16]>, OpSize16;
335 "idiv{w}\t$src", []>, OpSize16, SchedLoadReg<WriteIDiv16>;
361 (implicit EFLAGS)]>, OpSize16;
380 (implicit EFLAGS)]>, OpSize16;
401 [(set GR16:$dst, (not GR16:$src1))]>, OpSize16;
416 OpSize16;
448 OpSize16;
461 OpSize16, Requires<[Not64BitMode]>;
475 (implicit EFLAGS)]>, OpSize16;
495 OpSize16;
508 OpSize16, Requires<[Not64BitMode]>;
523 (implicit EFLAGS)]>, OpSize16;
612 1, OpSize16, 0>;