Lines Matching refs:AX

56 // AL is really implied by AX, but the registers in Defs must match the
59 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
66 // AX,DX = AX*GR16
67 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
84 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
92 // AX,DX = AX*[mem16]
94 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
110 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
113 // AX,DX = AX*GR16
114 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
128 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
131 // AX,DX = AX*[mem16]
132 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
283 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
284 def DIV8r  : I<0xF6, MRM6r, (outs),  (ins GR8:$src),    // AX/r8 = AL,AH
286 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
287 def DIV16r : I<0xF7, MRM6r, (outs),  (ins GR16:$src),   // DX:AX/r16 = AX,DX
298 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
299 def DIV8m  : I<0xF6, MRM6m, (outs), (ins i8mem:$src),   // AX/[mem8] = AL,AH
301 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
302 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src),  // DX:AX/[mem16] = AX,DX
315 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
316 def IDIV8r : I<0xF6, MRM7r, (outs),  (ins GR8:$src),    // AX/r8 = AL,AH
318 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
319 def IDIV16r: I<0xF7, MRM7r, (outs),  (ins GR16:$src),   // DX:AX/r16 = AX,DX
330 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
331 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src),   // AX/[mem8] = AL,AH
333 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
334 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src),  // DX:AX/[mem16] = AX,DX
1020   def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
1105   def NAME#16i16 : BinOpAI_RFF<BaseOpc4, mnemonic, Xi16, AX,
1185   def NAME#16i16 : BinOpAI_F<BaseOpc4, mnemonic, Xi16, AX,
1432   def TEST16i16  : BinOpAI_F<0xA8, "test", Xi16, AX,