Lines Matching refs:getPrimitiveSizeInBits

206   unsigned BitWidth = SVT->getPrimitiveSizeInBits();  in simplifyX86immShift()
231     assert(AmtVT->isVectorTy() && AmtVT->getPrimitiveSizeInBits() == 128 &&  in simplifyX86immShift()
258   assert(AmtVT->isVectorTy() && AmtVT->getPrimitiveSizeInBits() == 128 &&  in simplifyX86immShift()
448   unsigned NumLanes = ResTy->getPrimitiveSizeInBits() / 128;  in simplifyX86pack()
1347     assert(Arg1->getType()->getPrimitiveSizeInBits() == 128 &&  in instCombineIntrinsic()
1466     assert(Op0->getType()->getPrimitiveSizeInBits() == 128 &&  in instCombineIntrinsic()
1467            Op1->getType()->getPrimitiveSizeInBits() == 128 && VWidth0 == 2 &&  in instCombineIntrinsic()
1506     assert(Op0->getType()->getPrimitiveSizeInBits() == 128 && VWidth == 2 &&  in instCombineIntrinsic()
1530     assert(Op0->getType()->getPrimitiveSizeInBits() == 128 &&  in instCombineIntrinsic()
1531            Op1->getType()->getPrimitiveSizeInBits() == 128 && VWidth == 2 &&  in instCombineIntrinsic()
1567     assert(Op0->getType()->getPrimitiveSizeInBits() == 128 &&  in instCombineIntrinsic()
1568            Op1->getType()->getPrimitiveSizeInBits() == 128 && VWidth0 == 2 &&  in instCombineIntrinsic()
1633       assert(Mask->getType()->getPrimitiveSizeInBits() ==  in instCombineIntrinsic()
1634                  II.getType()->getPrimitiveSizeInBits() &&  in instCombineIntrinsic()
1966     unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128;  in simplifyDemandedVectorEltsIntrinsic()