Lines Matching refs:widenSubVector
6460 static SDValue widenSubVector(MVT VT, SDValue Vec, bool ZeroNewElements, in widenSubVector() function
6474 static SDValue widenSubVector(SDValue Vec, bool ZeroNewElements, in widenSubVector() function
6483 return widenSubVector(VT, Vec, ZeroNewElements, Subtarget, DAG, dl); in widenSubVector()
6714 Op = widenSubVector(Op, false, Subtarget, DAG, DL, 512); in getAVX512Node()
10746 IndicesVec = widenSubVector(IndicesVec, false, Subtarget, DAG, in createVariablePermute()
10762 IndicesVec = widenSubVector(IndicesVT.getSimpleVT(), IndicesVec, false, in createVariablePermute()
10771 SrcVec = widenSubVector(VT, SrcVec, false, Subtarget, DAG, SDLoc(SrcVec)); in createVariablePermute()
10918 SrcVec = widenSubVector(WidenSrcVT, SrcVec, false, Subtarget, DAG, in createVariablePermute()
10920 IndicesVec = widenSubVector(MVT::v8i64, IndicesVec, false, Subtarget, in createVariablePermute()
11105 return widenSubVector(VT, NewBV, !UndefUpper, Subtarget, DAG, dl); in LowerBUILD_VECTOR()
12338 return widenSubVector(Trunc, ZeroUppers, Subtarget, DAG, DL, in getAVX512TruncNode()
12345 SDValue NewSrc = widenSubVector(Src, ZeroUppers, Subtarget, DAG, DL, 512); in getAVX512TruncNode()
12353 Trunc = widenSubVector(Trunc, ZeroUppers, Subtarget, DAG, DL, in getAVX512TruncNode()
16155 V1 = widenSubVector(V1, false, Subtarget, DAG, DL, 512); in lowerShuffleWithPERMV()
16156 V2 = widenSubVector(V2, false, Subtarget, DAG, DL, 512); in lowerShuffleWithPERMV()
16167 MaskNode = widenSubVector(MaskNode, false, Subtarget, DAG, DL, 512); in lowerShuffleWithPERMV()
37895 Op = widenSubVector(Op, false, Subtarget, DAG, DL, VT.getSizeInBits()); in combineX86ShuffleChain()
37980 return widenSubVector(Res, UseZero, Subtarget, DAG, DL, RootSizeInBits); in combineX86ShuffleChain()
38051 return widenSubVector(Res, Mask[1] == SM_SentinelZero, Subtarget, DAG, DL, in combineX86ShuffleChain()
38316 Res = widenSubVector(Res, true, Subtarget, DAG, DL, RootSizeInBits); in combineX86ShuffleChain()
39381 Op = widenSubVector(Op, false, Subtarget, DAG, SDLoc(Op), in combineX86ShufflesRecursively()
41323 Src = widenSubVector(VT.getSimpleVT(), Src, false, Subtarget, TLO.DAG, in SimplifyDemandedVectorEltsForTargetNode()