Lines Matching refs:Zeroable
6199 const APInt &Zeroable, in canWidenShuffleElements() argument
6206 assert(!Zeroable.isZero() && "V2's non-undef elements are used?!"); in canWidenShuffleElements()
6208 if (Mask[i] != SM_SentinelUndef && Zeroable[i]) in canWidenShuffleElements()
8959 std::bitset<4> Zeroable, Undefs; in LowerBuildVectorv4x32() local
8963 Zeroable[i] = (Elt.isUndef() || X86::isZeroNode(Elt)); in LowerBuildVectorv4x32()
8965 assert(Zeroable.size() - Zeroable.count() > 1 && in LowerBuildVectorv4x32()
8973 if (Zeroable[i]) in LowerBuildVectorv4x32()
8998 if (Zeroable[EltIdx]) { in LowerBuildVectorv4x32()
9014 SDValue VZeroOrUndef = (Zeroable == Undefs) in LowerBuildVectorv4x32()
9032 if (Zeroable[i]) in LowerBuildVectorv4x32()
9052 unsigned ZMask = Zeroable.to_ulong(); in LowerBuildVectorv4x32()
12026 static bool isNonZeroElementsInOrder(const APInt &Zeroable, in isNonZeroElementsInOrder() argument
12036 if (Zeroable[i]) in isNonZeroElementsInOrder()
12054 SDValue V2, const APInt &Zeroable, in lowerShuffleWithPSHUFB() argument
12077 if (Zeroable[i / NumEltBytes]) { in lowerShuffleWithPSHUFB()
12111 const APInt &Zeroable, in lowerShuffleToEXPAND() argument
12116 if (!isNonZeroElementsInOrder(Zeroable, Mask, V1.getValueType(), in lowerShuffleToEXPAND()
12119 unsigned VEXPANDMask = (~Zeroable).getZExtValue(); in lowerShuffleToEXPAND()
12276 ArrayRef<int> Mask, const APInt &Zeroable, in matchShuffleAsVTRUNC() argument
12293 if (!Zeroable.extractBits(UpperElts, NumSrcElts).isAllOnes()) in matchShuffleAsVTRUNC()
12376 const APInt &Zeroable, in lowerShuffleWithVPMOV() argument
12390 !Zeroable.extractBits(UpperElts, NumSrcElts).isAllOnes()) in lowerShuffleWithVPMOV()
12419 const APInt &Zeroable, in lowerShuffleAsVTRUNC() argument
12447 !Zeroable.extractBits(UpperElts, NumSrcElts).isAllOnes()) in lowerShuffleAsVTRUNC()
12664 const APInt &Zeroable, in lowerShuffleAsBitMask() argument
12692 if (Zeroable[i]) in lowerShuffleAsBitMask()
12745 const APInt &Zeroable, bool &ForceV1Zero, in matchShuffleAsBlend() argument
12773 if (Zeroable[i]) { in matchShuffleAsBlend()
12808 const APInt &Zeroable, in lowerShuffleAsBlend() argument
12814 if (!matchShuffleAsBlend(V1, V2, Mask, Zeroable, ForceV1Zero, ForceV2Zero, in lowerShuffleAsBlend()
12879 if (SDValue Masked = lowerShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable, in lowerShuffleAsBlend()
12946 if (SDValue Masked = lowerShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable, in lowerShuffleAsBlend()
13554 const APInt &Zeroable, in lowerShuffleAsByteShiftMask() argument
13562 unsigned ZeroLo = Zeroable.countTrailingOnes(); in lowerShuffleAsByteShiftMask()
13563 unsigned ZeroHi = Zeroable.countLeadingOnes(); in lowerShuffleAsByteShiftMask()
13641 int MaskOffset, const APInt &Zeroable, in matchShuffleAsShift() argument
13649 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))]) in matchShuffleAsShift()
13703 const APInt &Zeroable, in lowerShuffleAsShift() argument
13715 Mask, 0, Zeroable, Subtarget); in lowerShuffleAsShift()
13720 Mask, Size, Zeroable, Subtarget); in lowerShuffleAsShift()
13739 uint64_t &BitIdx, const APInt &Zeroable) { in matchShuffleAsEXTRQ() argument
13743 assert(!Zeroable.isAllOnes() && "Fully zeroable shuffle mask"); in matchShuffleAsEXTRQ()
13753 if (!Zeroable[Len - 1]) in matchShuffleAsEXTRQ()
13861 const APInt &Zeroable, SelectionDAG &DAG) { in lowerShuffleWithSSE4A() argument
13863 if (matchShuffleAsEXTRQ(VT, V1, V2, Mask, BitLen, BitIdx, Zeroable)) in lowerShuffleWithSSE4A()
14050 const APInt &Zeroable, const X86Subtarget &Subtarget, in lowerShuffleAsZeroOrAnyExtend() argument
14073 if (!Zeroable[i]) in lowerShuffleAsZeroOrAnyExtend()
14145 if (!Zeroable[i]) in lowerShuffleAsZeroOrAnyExtend()
14216 const APInt &Zeroable, const X86Subtarget &Subtarget, in lowerShuffleAsElementInsertion() argument
14229 if (i != V2Index && !Zeroable[i]) { in lowerShuffleAsElementInsertion()
14644 const APInt &Zeroable, in matchShuffleAsInsertPS() argument
14662 if (Zeroable[i]) { in matchShuffleAsInsertPS()
14731 ArrayRef<int> Mask, const APInt &Zeroable, in lowerShuffleAsInsertPS() argument
14738 if (!matchShuffleAsInsertPS(V1, V2, InsertPSMask, Zeroable, Mask, DAG)) in lowerShuffleAsInsertPS()
14871 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV2F64Shuffle() argument
14913 DL, MVT::v2f64, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV2F64Shuffle()
14920 DL, MVT::v2f64, V2, V1, InverseMask, Zeroable, Subtarget, DAG)) in lowerV2F64Shuffle()
14936 Zeroable, Subtarget, DAG)) in lowerV2F64Shuffle()
14955 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV2I64Shuffle() argument
14992 Zeroable, Subtarget, DAG)) in lowerV2I64Shuffle()
14998 DL, MVT::v2i64, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV2I64Shuffle()
15004 DL, MVT::v2i64, V2, V1, InverseMask, Zeroable, Subtarget, DAG)) in lowerV2I64Shuffle()
15012 Zeroable, Subtarget, DAG)) in lowerV2I64Shuffle()
15146 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV4F32Shuffle() argument
15202 DL, MVT::v4f32, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV4F32Shuffle()
15207 Zeroable, Subtarget, DAG)) in lowerV4F32Shuffle()
15211 if (SDValue V = lowerShuffleAsInsertPS(DL, V1, V2, Mask, Zeroable, DAG)) in lowerV4F32Shuffle()
15242 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV4I32Shuffle() argument
15253 Zeroable, Subtarget, DAG)) in lowerV4I32Shuffle()
15288 Zeroable, Subtarget, DAG)) in lowerV4I32Shuffle()
15294 DL, MVT::v4i32, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV4I32Shuffle()
15302 Zeroable, Subtarget, DAG)) in lowerV4I32Shuffle()
15306 Zeroable, Subtarget, DAG)) in lowerV4I32Shuffle()
15865 const APInt &Zeroable, SelectionDAG &DAG, bool &V1InUse, bool &V2InUse) { in lowerShuffleAsBlendOfPSHUFBs() argument
15886 if (Zeroable[i / Scale]) in lowerShuffleAsBlendOfPSHUFBs()
15927 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV8I16Shuffle() argument
15937 Zeroable, Subtarget, DAG)) in lowerV8I16Shuffle()
15941 if (SDValue V = lowerShuffleWithVPMOV(DL, MVT::v8i16, V1, V2, Mask, Zeroable, in lowerV8I16Shuffle()
15950 Zeroable, Subtarget, DAG)) in lowerV8I16Shuffle()
15989 Zeroable, Subtarget, DAG)) in lowerV8I16Shuffle()
15995 Zeroable, DAG)) in lowerV8I16Shuffle()
16001 DL, MVT::v8i16, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV8I16Shuffle()
16009 Zeroable, Subtarget, DAG)) in lowerV8I16Shuffle()
16013 Zeroable, Subtarget, DAG)) in lowerV8I16Shuffle()
16026 if (SDValue V = lowerShuffleAsVTRUNC(DL, MVT::v8i16, V1, V2, Mask, Zeroable, in lowerV8I16Shuffle()
16041 Zeroable, Subtarget, DAG)) in lowerV8I16Shuffle()
16106 Zeroable, DAG, V1InUse, V2InUse); in lowerV8I16Shuffle()
16117 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV8F16Shuffle() argument
16134 DL, MVT::v8f16, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV8F16Shuffle()
16192 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV16I8Shuffle() argument
16201 Zeroable, Subtarget, DAG)) in lowerV16I8Shuffle()
16216 Zeroable, Subtarget, DAG)) in lowerV16I8Shuffle()
16220 if (SDValue V = lowerShuffleWithVPMOV(DL, MVT::v16i8, V1, V2, Mask, Zeroable, in lowerV16I8Shuffle()
16224 if (SDValue V = lowerShuffleAsVTRUNC(DL, MVT::v16i8, V1, V2, Mask, Zeroable, in lowerV16I8Shuffle()
16231 Zeroable, DAG)) in lowerV16I8Shuffle()
16350 Zeroable, Subtarget, DAG)) in lowerV16I8Shuffle()
16359 Zeroable, Subtarget, DAG)) in lowerV16I8Shuffle()
16387 DL, MVT::v16i8, V1, V2, Mask, Zeroable, DAG, V1InUse, V2InUse); in lowerV16I8Shuffle()
16395 Zeroable, Subtarget, DAG)) in lowerV16I8Shuffle()
16434 DL, MVT::v16i8, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV16I8Shuffle()
16548 const APInt &Zeroable, in lower128BitShuffle() argument
16553 return lowerV2I64Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower128BitShuffle()
16555 return lowerV2F64Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower128BitShuffle()
16557 return lowerV4I32Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower128BitShuffle()
16559 return lowerV4F32Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower128BitShuffle()
16561 return lowerV8I16Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower128BitShuffle()
16563 return lowerV8F16Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower128BitShuffle()
16565 return lowerV16I8Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower128BitShuffle()
16936 const APInt &Zeroable, in lowerV2X128Shuffle() argument
16961 if (!canWidenShuffleElements(Mask, Zeroable, V2IsZero, WidenedMask)) in lowerV2X128Shuffle()
16964 bool IsLowZero = (Zeroable & 0x3) == 0x3; in lowerV2X128Shuffle()
16965 bool IsHighZero = (Zeroable & 0xc) == 0xc; in lowerV2X128Shuffle()
16982 if (SDValue Blend = lowerShuffleAsBlend(DL, VT, V1, V2, Mask, Zeroable, in lowerV2X128Shuffle()
17630 const APInt &Zeroable) { in matchShuffleWithSHUFPD() argument
17640 ZeroLane[i & 1] &= Zeroable[i]; in matchShuffleWithSHUFPD()
17674 const APInt &Zeroable, in lowerShuffleWithSHUFPD() argument
17683 Mask, Zeroable)) in lowerShuffleWithSHUFPD()
17702 const APInt &Zeroable, in lowerShuffleAsVTRUNCAndUnpack() argument
17711 if (Zeroable.countLeadingOnes() < (Mask.size() - 8)) in lowerShuffleAsVTRUNCAndUnpack()
17737 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV4F64Shuffle() argument
17744 if (SDValue V = lowerV2X128Shuffle(DL, MVT::v4f64, V1, V2, Mask, Zeroable, in lowerV4F64Shuffle()
17793 Zeroable, Subtarget, DAG)) in lowerV4F64Shuffle()
17798 Zeroable, Subtarget, DAG)) in lowerV4F64Shuffle()
17837 if (SDValue V = lowerShuffleToEXPAND(DL, MVT::v4f64, Zeroable, Mask, V1, V2, in lowerV4F64Shuffle()
17857 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV4I64Shuffle() argument
17865 if (SDValue V = lowerV2X128Shuffle(DL, MVT::v4i64, V1, V2, Mask, Zeroable, in lowerV4I64Shuffle()
17870 Zeroable, Subtarget, DAG)) in lowerV4I64Shuffle()
17900 Zeroable, Subtarget, DAG)) in lowerV4I64Shuffle()
17909 if (SDValue V = lowerShuffleToEXPAND(DL, MVT::v4i64, Zeroable, Mask, V1, V2, in lowerV4I64Shuffle()
17962 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV8F32Shuffle() argument
17970 Zeroable, Subtarget, DAG)) in lowerV8F32Shuffle()
18034 if (SDValue V = lowerShuffleToEXPAND(DL, MVT::v8f32, Zeroable, Mask, V1, V2, in lowerV8F32Shuffle()
18061 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV8I32Shuffle() argument
18073 Zeroable, Subtarget, DAG)) in lowerV8I32Shuffle()
18085 Zeroable, Subtarget, DAG)) in lowerV8I32Shuffle()
18112 Zeroable, Subtarget, DAG)) in lowerV8I32Shuffle()
18121 if (SDValue V = lowerShuffleToEXPAND(DL, MVT::v8i32, Zeroable, Mask, V1, V2, in lowerV8I32Shuffle()
18176 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV16I16Shuffle() argument
18188 DL, MVT::v16i16, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV16I16Shuffle()
18197 Zeroable, Subtarget, DAG)) in lowerV16I16Shuffle()
18210 if (SDValue V = lowerShuffleAsVTRUNC(DL, MVT::v16i16, V1, V2, Mask, Zeroable, in lowerV16I16Shuffle()
18216 Zeroable, Subtarget, DAG)) in lowerV16I16Shuffle()
18263 Zeroable, Subtarget, DAG)) in lowerV16I16Shuffle()
18291 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV32I8Shuffle() argument
18303 Zeroable, Subtarget, DAG)) in lowerV32I8Shuffle()
18312 Zeroable, Subtarget, DAG)) in lowerV32I8Shuffle()
18325 if (SDValue V = lowerShuffleAsVTRUNC(DL, MVT::v32i8, V1, V2, Mask, Zeroable, in lowerV32I8Shuffle()
18331 Zeroable, Subtarget, DAG)) in lowerV32I8Shuffle()
18368 Zeroable, Subtarget, DAG)) in lowerV32I8Shuffle()
18391 Mask, Zeroable, DAG)) in lowerV32I8Shuffle()
18405 SDValue V1, SDValue V2, const APInt &Zeroable, in lower256BitShuffle() argument
18415 DL, VT, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lower256BitShuffle()
18434 if (SDValue V = lowerShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable, in lower256BitShuffle()
18458 return lowerV4F64Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower256BitShuffle()
18460 return lowerV4I64Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower256BitShuffle()
18462 return lowerV8F32Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower256BitShuffle()
18464 return lowerV8I32Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower256BitShuffle()
18466 return lowerV16I16Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower256BitShuffle()
18468 return lowerV32I8Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower256BitShuffle()
18477 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV4X128Shuffle() argument
18494 if (Widened128Mask[0] == 0 && (Zeroable & 0xf0) == 0xf0 && in lowerV4X128Shuffle()
18495 (Widened128Mask[1] == 1 || (Zeroable & 0x0c) == 0x0c)) { in lowerV4X128Shuffle()
18496 unsigned NumElts = ((Zeroable & 0x0c) == 0x0c) ? 2 : 4; in lowerV4X128Shuffle()
18585 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV8F64Shuffle() argument
18614 if (SDValue Shuf128 = lowerV4X128Shuffle(DL, MVT::v8f64, Mask, Zeroable, V1, in lowerV8F64Shuffle()
18623 Zeroable, Subtarget, DAG)) in lowerV8F64Shuffle()
18626 if (SDValue V = lowerShuffleToEXPAND(DL, MVT::v8f64, Zeroable, Mask, V1, V2, in lowerV8F64Shuffle()
18631 Zeroable, Subtarget, DAG)) in lowerV8F64Shuffle()
18639 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV16F32Shuffle() argument
18667 Zeroable, Subtarget, DAG)) in lowerV16F32Shuffle()
18689 if (SDValue V = lowerShuffleToEXPAND(DL, MVT::v16f32, Zeroable, Mask, in lowerV16F32Shuffle()
18698 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV8I64Shuffle() argument
18726 if (SDValue Shuf128 = lowerV4X128Shuffle(DL, MVT::v8i64, Mask, Zeroable, V1, in lowerV8I64Shuffle()
18732 Zeroable, Subtarget, DAG)) in lowerV8I64Shuffle()
18750 if (SDValue V = lowerShuffleToEXPAND(DL, MVT::v8i64, Zeroable, Mask, V1, V2, in lowerV8I64Shuffle()
18755 Zeroable, Subtarget, DAG)) in lowerV8I64Shuffle()
18763 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV16I32Shuffle() argument
18774 DL, MVT::v16i32, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV16I32Shuffle()
18796 Zeroable, Subtarget, DAG)) in lowerV16I32Shuffle()
18827 if (SDValue V = lowerShuffleToEXPAND(DL, MVT::v16i32, Zeroable, Mask, V1, V2, in lowerV16I32Shuffle()
18832 Zeroable, Subtarget, DAG)) in lowerV16I32Shuffle()
18840 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV32I16Shuffle() argument
18852 DL, MVT::v32i16, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV32I16Shuffle()
18866 Zeroable, Subtarget, DAG)) in lowerV32I16Shuffle()
18891 Zeroable, Subtarget, DAG)) in lowerV32I16Shuffle()
18895 Zeroable, Subtarget, DAG)) in lowerV32I16Shuffle()
18903 const APInt &Zeroable, SDValue V1, SDValue V2, in lowerV64I8Shuffle() argument
18915 DL, MVT::v64i8, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lowerV64I8Shuffle()
18929 Zeroable, Subtarget, DAG)) in lowerV64I8Shuffle()
18945 Zeroable, Subtarget, DAG)) in lowerV64I8Shuffle()
18949 Zeroable, Subtarget, DAG)) in lowerV64I8Shuffle()
18963 Zeroable, Subtarget, DAG)) in lowerV64I8Shuffle()
18976 return lowerShuffleAsBlendOfPSHUFBs(DL, MVT::v64i8, V1, V2, Mask, Zeroable, in lowerV64I8Shuffle()
19001 const APInt &Zeroable, in lower512BitShuffle() argument
19014 DL, VT, V1, V2, Mask, Zeroable, Subtarget, DAG)) in lower512BitShuffle()
19030 if (SDValue V = lowerShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable, in lower512BitShuffle()
19052 return lowerV8F64Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower512BitShuffle()
19054 return lowerV16F32Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower512BitShuffle()
19056 return lowerV8I64Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower512BitShuffle()
19058 return lowerV16I32Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower512BitShuffle()
19060 return lowerV32I16Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower512BitShuffle()
19062 return lowerV64I8Shuffle(DL, Mask, Zeroable, V1, V2, Subtarget, DAG); in lower512BitShuffle()
19116 int MaskOffset, const APInt &Zeroable) { in match1BitShuffleAsKSHIFT() argument
19121 if (!Zeroable[j + (Left ? 0 : (Size - Shift))]) in match1BitShuffleAsKSHIFT()
19151 const APInt &Zeroable, in lower1BitShuffle() argument
19181 if ((int)Zeroable.countLeadingOnes() >= (NumElts - SubvecElts)) { in lower1BitShuffle()
19201 int ShiftAmt = match1BitShuffleAsKSHIFT(Opcode, Mask, Offset, Zeroable); in lower1BitShuffle()
19416 APInt Zeroable = KnownUndef | KnownZero; in lowerVECTOR_SHUFFLE() local
19417 if (Zeroable.isAllOnes()) in lowerVECTOR_SHUFFLE()
19428 canWidenShuffleElements(OrigMask, Zeroable, V2IsZero, WidenedMask)) { in lowerVECTOR_SHUFFLE()
19491 return lower128BitShuffle(DL, Mask, VT, V1, V2, Zeroable, Subtarget, DAG); in lowerVECTOR_SHUFFLE()
19494 return lower256BitShuffle(DL, Mask, VT, V1, V2, Zeroable, Subtarget, DAG); in lowerVECTOR_SHUFFLE()
19497 return lower512BitShuffle(DL, Mask, VT, V1, V2, Zeroable, Subtarget, DAG); in lowerVECTOR_SHUFFLE()
19500 return lower1BitShuffle(DL, Mask, VT, V1, V2, Zeroable, Subtarget, DAG); in lowerVECTOR_SHUFFLE()
37397 const APInt &Zeroable, in matchUnaryPermuteShuffle() argument
37506 Mask, 0, Zeroable, Subtarget); in matchUnaryPermuteShuffle()
37700 MVT MaskVT, ArrayRef<int> Mask, const APInt &Zeroable, in matchBinaryPermuteShuffle() argument
37746 if (matchShuffleAsBlend(V1, V2, TargetMask, Zeroable, ForceV1Zero, in matchBinaryPermuteShuffle()
37780 matchShuffleAsInsertPS(V1, V2, PermuteImm, Zeroable, Mask, DAG)) { in matchBinaryPermuteShuffle()
37793 PermuteImm, Mask, Zeroable)) { in matchBinaryPermuteShuffle()
37852 matchShuffleAsInsertPS(V1, V2, PermuteImm, Zeroable, Mask, DAG)) { in matchBinaryPermuteShuffle()
38155 APInt Zeroable = KnownUndef | KnownZero; in combineX86ShuffleChain() local
38194 if (matchUnaryPermuteShuffle(MaskVT, Mask, Zeroable, AllowFloatDomain, in combineX86ShuffleChain()
38216 if (matchShuffleAsInsertPS(SrcV1, SrcV2, PermuteImm, Zeroable, Mask, in combineX86ShuffleChain()
38259 if (matchBinaryPermuteShuffle(MaskVT, Mask, Zeroable, AllowFloatDomain, in combineX86ShuffleChain()
38280 Zeroable)) { in combineX86ShuffleChain()
38305 if (matchShuffleAsVTRUNC(ShuffleSrcVT, ShuffleVT, IntMaskVT, Mask, Zeroable, in combineX86ShuffleChain()