Lines Matching refs:SSECC
24079 unsigned SSECC; in translateX86FSETCC() local
24094 case ISD::SETEQ: SSECC = 0; break; in translateX86FSETCC()
24098 case ISD::SETOLT: SSECC = 1; break; in translateX86FSETCC()
24102 case ISD::SETOLE: SSECC = 2; break; in translateX86FSETCC()
24103 case ISD::SETUO: SSECC = 3; break; in translateX86FSETCC()
24105 case ISD::SETNE: SSECC = 4; break; in translateX86FSETCC()
24107 case ISD::SETUGE: SSECC = 5; break; in translateX86FSETCC()
24109 case ISD::SETUGT: SSECC = 6; break; in translateX86FSETCC()
24110 case ISD::SETO: SSECC = 7; break; in translateX86FSETCC()
24111 case ISD::SETUEQ: SSECC = 8; break; in translateX86FSETCC()
24112 case ISD::SETONE: SSECC = 12; break; in translateX86FSETCC()
24133 return SSECC; in translateX86FSETCC()
24315 unsigned SSECC = translateX86FSETCC(Cond, Op0, Op1, IsAlwaysSignaling); in LowerVSETCC() local
24378 {Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)}); in LowerVSETCC()
24382 Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)); in LowerVSETCC()
24388 SSECC |= (IsAlwaysSignaling ^ IsSignaling) << 4; in LowerVSETCC()
24391 {Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)}); in LowerVSETCC()
24395 Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)); in LowerVSETCC()
25056 unsigned SSECC = in LowerSELECT() local
25063 DAG.getTargetConstant(SSECC, DL, MVT::i8)); in LowerSELECT()
25068 if (SSECC < 8 || Subtarget.hasAVX()) { in LowerSELECT()
25070 DAG.getTargetConstant(SSECC, DL, MVT::i8)); in LowerSELECT()