Lines Matching refs:RootSizeInBits
19356 unsigned RootSizeInBits, const SDLoc &DL, SelectionDAG &DAG,
37889 unsigned RootSizeInBits = RootVT.getSizeInBits(); in combineX86ShuffleChain() local
37910 assert((RootSizeInBits % VT1.getSizeInBits()) == 0 && in combineX86ShuffleChain()
37911 (RootSizeInBits % VT2.getSizeInBits()) == 0 && "Vector size mismatch"); in combineX86ShuffleChain()
37922 unsigned BaseMaskEltSizeInBits = RootSizeInBits / NumBaseMaskElts; in combineX86ShuffleChain()
37931 if (RootSizeInBits == 512 || (Subtarget.hasVLX() && RootSizeInBits >= 128)) { in combineX86ShuffleChain()
37942 V1.getValueSizeInBits() >= RootSizeInBits && in combineX86ShuffleChain()
37952 if (VT1 == VT2 && VT1.getSizeInBits() == RootSizeInBits && VT1.isVector()) { in combineX86ShuffleChain()
37980 return widenSubVector(Res, UseZero, Subtarget, DAG, DL, RootSizeInBits); in combineX86ShuffleChain()
38129 unsigned MaskEltSizeInBits = RootSizeInBits / NumMaskElts; in combineX86ShuffleChain()
38211 if (!UnaryShuffle && AllowFloatDomain && RootSizeInBits == 128 && in combineX86ShuffleChain()
38277 if (Subtarget.hasSSE4A() && AllowIntDomain && RootSizeInBits == 128) { in combineX86ShuffleChain()
38315 if (ShuffleVT.getSizeInBits() < RootSizeInBits) in combineX86ShuffleChain()
38316 Res = widenSubVector(Res, true, Subtarget, DAG, DL, RootSizeInBits); in combineX86ShuffleChain()
38321 if (RootSizeInBits < 512 && in combineX86ShuffleChain()
38636 unsigned RootSizeInBits = RootVT.getSizeInBits(); in combineX86ShuffleChainWithExtract() local
38637 assert((RootSizeInBits % NumMaskElts) == 0 && "Unexpected root shuffle mask"); in combineX86ShuffleChainWithExtract()
38640 if (llvm::any_of(Inputs, [RootSizeInBits](SDValue Input) { in combineX86ShuffleChainWithExtract()
38641 return Input.getValueSizeInBits() < RootSizeInBits; in combineX86ShuffleChainWithExtract()
38650 unsigned WideSizeInBits = RootSizeInBits; in combineX86ShuffleChainWithExtract()
38673 unsigned Scale = WideSizeInBits / RootSizeInBits; in combineX86ShuffleChainWithExtract()
38674 assert((WideSizeInBits % RootSizeInBits) == 0 && in combineX86ShuffleChainWithExtract()
38720 extractSubVector(WideShuffle, 0, DAG, SDLoc(Root), RootSizeInBits); in combineX86ShuffleChainWithExtract()
38730 unsigned RootSizeInBits, const SDLoc &DL, SelectionDAG &DAG, in canonicalizeShuffleMaskWithHorizOp() argument
38743 if (VT0.getSizeInBits() != RootSizeInBits || llvm::any_of(BC, [&](SDValue V) { in canonicalizeShuffleMaskWithHorizOp()
38765 unsigned EltSizeInBits = RootSizeInBits / Mask.size(); in canonicalizeShuffleMaskWithHorizOp()
38829 MVT ShuffleVT = MVT::getVectorVT(MVT::f32, RootSizeInBits / 32); in canonicalizeShuffleMaskWithHorizOp()
39055 unsigned RootSizeInBits = RootVT.getSizeInBits(); in combineX86ShufflesRecursively() local
39074 assert((RootSizeInBits % VT.getSizeInBits()) == 0 && in combineX86ShufflesRecursively()
39093 (RootSizeInBits % Op.getOperand(0).getValueSizeInBits()) == 0 && in combineX86ShufflesRecursively()
39108 if (RootSizeInBits > VT.getSizeInBits()) { in combineX86ShufflesRecursively()
39109 unsigned NumSubVecs = RootSizeInBits / VT.getSizeInBits(); in combineX86ShufflesRecursively()
39318 unsigned EltSizeInBits = RootSizeInBits / Mask.size(); in combineX86ShufflesRecursively()
39328 Ops, Mask, RootSizeInBits, SDLoc(Root), DAG, Subtarget)) in combineX86ShufflesRecursively()
39350 if (Op.getValueSizeInBits() < RootSizeInBits) { in combineX86ShufflesRecursively()
39353 unsigned EltSizeInBits = RootSizeInBits / NumExpectedVectorElts; in combineX86ShufflesRecursively()
39376 if (any_of(Ops, [RootSizeInBits](SDValue Op) { in combineX86ShufflesRecursively()
39377 return Op.getValueSizeInBits() < RootSizeInBits; in combineX86ShufflesRecursively()
39380 if (Op.getValueSizeInBits() < RootSizeInBits) in combineX86ShufflesRecursively()
39382 RootSizeInBits); in combineX86ShufflesRecursively()