7107       return DAG.getNode(X86ISD::PACKUS, dl, VT, LHS, RHS);  in getPack()
7125     return DAG.getNode(X86ISD::PACKUS, dl, VT, LHS, RHS);  in getPack()
8432   case X86ISD::PACKUS: {  in getFauxShuffleMask()
9997   case X86ISD::PACKUS:  in isHorizOp()
11806   case X86ISD::PACKUS:  in IsElementEquivalent()
12571         PackOpcode = X86ISD::PACKUS;  in matchShuffleWithPACK()
16074     SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v8i16, V1, V2);  in lowerV8I16Shuffle()
16077       Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v8i16, Result, Result);  in lowerV8I16Shuffle()
16092     return DAG.getNode(HasSSE41 ? X86ISD::PACKUS : X86ISD::PACKSS, DL,  in lowerV8I16Shuffle()
16466     SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1,  in lowerV16I8Shuffle()
16470       Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);  in lowerV16I8Shuffle()
16484     return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1,  in lowerV16I8Shuffle()
16539   return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);  in lowerV16I8Shuffle()
21946   assert((Opcode == X86ISD::PACKSS || Opcode == X86ISD::PACKUS) &&  in truncateVectorWithPACK()
22191             truncateVectorWithPACK(X86ISD::PACKUS, VT, In, DL, DAG, Subtarget))  in LowerTRUNCATE()
22273     return DAG.getNode(X86ISD::PACKUS, DL, VT, InLo, InHi);  in LowerTRUNCATE()
29894       return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);  in convertShiftLeftToScale()
30184     return DAG.getNode(X86ISD::PACKUS, dl, VT, LoR, HiR);  in LowerShift()
30292       return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);  in LowerShift()
30311     return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);  in LowerShift()
31338     V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,  in LowerHorizontalByteSum()
33605   NODE_NAME_CASE(PACKUS)  in getTargetNodeName()
36822   case X86ISD::PACKUS: {  in computeKnownBitsForTargetNode()
38330                          Root.getOpcode() == X86ISD::PACKUS))  in combineX86ShuffleChain()
38750   bool isPack = (Opcode0 == X86ISD::PACKSS || Opcode0 == X86ISD::PACKUS);  in canonicalizeShuffleMaskWithHorizOp()
41200   case X86ISD::PACKUS: {  in SimplifyDemandedVectorEltsForTargetNode()
41493     case X86ISD::PACKUS:  in SimplifyDemandedVectorEltsForTargetNode()
46878   assert((X86ISD::PACKSS == Opcode || X86ISD::PACKUS == Opcode) &&  in combineVectorPack()
48725       SDValue Mid = truncateVectorWithPACK(X86ISD::PACKUS, MVT::v16i16, USatVal,  in combineTruncateWithSat()
48757         SDValue V = truncateVectorWithPACK(X86ISD::PACKUS, VT, Mid, DL, DAG,  in combineTruncateWithSat()
48762         return truncateVectorWithPACK(X86ISD::PACKUS, VT, USatVal, DL, DAG,  in combineTruncateWithSat()
50161   return truncateVectorWithPACK(X86ISD::PACKUS, OutVT, In, DL, DAG, Subtarget);  in combineVectorTruncationWithPACKUS()
50282     return truncateVectorWithPACK(X86ISD::PACKUS, VT, In, DL, DAG, Subtarget);  in combineVectorSignBitsTruncation()
51870   if (N0.getOpcode() == X86ISD::PACKUS && N0.getValueSizeInBits() == 128 &&  in combineZext()
54089     case X86ISD::PACKUS:  in combineConcatVectorOps()
55114   case X86ISD::PACKUS:      return combineVectorPack(N, DAG, DCI, Subtarget);  in PerformDAGCombine()