7111       return DAG.getNode(X86ISD::PACKSS, dl, VT, LHS, RHS);  in getPack()
7134   return DAG.getNode(X86ISD::PACKSS, dl, VT, LHS, RHS);  in getPack()
8431   case X86ISD::PACKSS:  in getFauxShuffleMask()
8445     if (Opcode == X86ISD::PACKSS) {  in getFauxShuffleMask()
9996   case X86ISD::PACKSS:  in isHorizOp()
11805   case X86ISD::PACKSS:  in IsElementEquivalent()
12584       PackOpcode = X86ISD::PACKSS;  in matchShuffleWithPACK()
12636       (PackOpcode == X86ISD::PACKSS || Subtarget.hasSSE41()))  in lowerShuffleWithPACK()
16092     return DAG.getNode(HasSSE41 ? X86ISD::PACKUS : X86ISD::PACKSS, DL,  in lowerV8I16Shuffle()
21946   assert((Opcode == X86ISD::PACKSS || Opcode == X86ISD::PACKUS) &&  in truncateVectorWithPACK()
21981       (Opcode == X86ISD::PACKSS || Subtarget.hasSSE41())) {  in truncateVectorWithPACK()
22198             truncateVectorWithPACK(X86ISD::PACKSS, VT, In, DL, DAG, Subtarget))  in LowerTRUNCATE()
33604   NODE_NAME_CASE(PACKSS)  in getTargetNodeName()
37100   case X86ISD::PACKSS: {  in ComputeNumSignBitsForTargetNode()
38329                          Root.getOpcode() == X86ISD::PACKSS ||  in combineX86ShuffleChain()
38750   bool isPack = (Opcode0 == X86ISD::PACKSS || Opcode0 == X86ISD::PACKUS);  in canonicalizeShuffleMaskWithHorizOp()
41199   case X86ISD::PACKSS:  in SimplifyDemandedVectorEltsForTargetNode()
41492     case X86ISD::PACKSS:  in SimplifyDemandedVectorEltsForTargetNode()
41881   case X86ISD::PACKSS:  in SimplifyDemandedBitsForTargetNode()
42388       V = DAG.getNode(X86ISD::PACKSS, DL, MVT::v16i8, V,  in combineBitcastvxi1()
45662   if (Vec.getOpcode() == X86ISD::PACKSS && VecVT == MVT::v16i8) {  in combineSetCCMOVMSK()
46878   assert((X86ISD::PACKSS == Opcode || X86ISD::PACKUS == Opcode) &&  in combineVectorPack()
46891   bool IsSigned = (X86ISD::PACKSS == Opcode);  in combineVectorPack()
48754         SDValue Mid = truncateVectorWithPACK(X86ISD::PACKSS, MidVT, USatVal, DL,  in combineTruncateWithSat()
48766       return truncateVectorWithPACK(X86ISD::PACKSS, VT, SSatVal, DL, DAG,  in combineTruncateWithSat()
50173   return truncateVectorWithPACK(X86ISD::PACKSS, OutVT, In, DL, DAG, Subtarget);  in combineVectorTruncationWithPACKSS()
50296     return truncateVectorWithPACK(X86ISD::PACKSS, VT, In, DL, DAG, Subtarget);  in combineVectorSignBitsTruncation()
50306         return truncateVectorWithPACK(X86ISD::PACKSS, VT, NewIn, DL, DAG,  in combineVectorSignBitsTruncation()
54088     case X86ISD::PACKSS:  in combineConcatVectorOps()
55113   case X86ISD::PACKSS:  in PerformDAGCombine()