12676   MVT LogicVT = VT;  in lowerShuffleAsBitMask()  local
12682     LogicVT =  in lowerShuffleAsBitMask()
12707   VMask = DAG.getBitcast(LogicVT, VMask);  in lowerShuffleAsBitMask()
12708   V = DAG.getBitcast(LogicVT, V);  in lowerShuffleAsBitMask()
12709   SDValue And = DAG.getNode(ISD::AND, DL, LogicVT, V, VMask);  in lowerShuffleAsBitMask()
23216   MVT LogicVT = VT;  in LowerFABSorFNEG()  local
23218     LogicVT = (VT == MVT::f64)   ? MVT::v2f64  in LowerFABSorFNEG()
23227   SDValue Mask = DAG.getConstantFP(APFloat(Sem, MaskElt), dl, LogicVT);  in LowerFABSorFNEG()
23237     return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);  in LowerFABSorFNEG()
23241   Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);  in LowerFABSorFNEG()
23242   SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);  in LowerFABSorFNEG()
23277   MVT LogicVT = VT;  in LowerFCOPYSIGN()  local
23279     LogicVT = (VT == MVT::f64)   ? MVT::v2f64  in LowerFCOPYSIGN()
23286       APFloat(Sem, APInt::getSignMask(EltSizeInBits)), dl, LogicVT);  in LowerFCOPYSIGN()
23288       APFloat(Sem, APInt::getSignedMaxValue(EltSizeInBits)), dl, LogicVT);  in LowerFCOPYSIGN()
23292     Sign = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Sign);  in LowerFCOPYSIGN()
23293   SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Sign, SignMask);  in LowerFCOPYSIGN()
23302     MagBits = DAG.getConstantFP(APF, dl, LogicVT);  in LowerFCOPYSIGN()
23306       Mag = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Mag);  in LowerFCOPYSIGN()
23307     MagBits = DAG.getNode(X86ISD::FAND, dl, LogicVT, Mag, MagMask);  in LowerFCOPYSIGN()
23311   SDValue Or = DAG.getNode(X86ISD::FOR, dl, LogicVT, MagBits, SignBit);  in LowerFCOPYSIGN()