Lines Matching refs:IdxVal
6377 static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, in extractSubVector() argument
6391 IdxVal &= ~(ElemsPerChunk - 1); in extractSubVector()
6396 Vec->ops().slice(IdxVal, ElemsPerChunk)); in extractSubVector()
6398 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl); in extractSubVector()
6408 static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal, in extract128BitVector() argument
6412 return extractSubVector(Vec, IdxVal, DAG, dl, 128); in extract128BitVector()
6416 static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal, in extract256BitVector() argument
6419 return extractSubVector(Vec, IdxVal, DAG, dl, 256); in extract256BitVector()
6422 static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal, in insertSubVector() argument
6440 IdxVal &= ~(ElemsPerChunk - 1); in insertSubVector()
6442 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl); in insertSubVector()
6452 static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, in insert128BitVector() argument
6455 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128); in insert128BitVector()
6733 unsigned IdxVal = Op.getConstantOperandVal(2); in insert1BitVector() local
6739 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal in insert1BitVector()
6753 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode())) { in insert1BitVector()
6763 assert(IdxVal + SubVecNumElems <= NumElems && in insert1BitVector()
6764 IdxVal % SubVecVT.getSizeInBits() == 0 && in insert1BitVector()
6769 if (IdxVal == 0) { in insert1BitVector()
6788 assert(IdxVal != 0 && "Unexpected index"); in insert1BitVector()
6790 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in insert1BitVector()
6795 assert(IdxVal != 0 && "Unexpected index"); in insert1BitVector()
6797 if (llvm::all_of(Vec->ops().slice(IdxVal + SubVecNumElems), in insert1BitVector()
6800 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in insert1BitVector()
6804 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal; in insert1BitVector()
6815 if (IdxVal + SubVecNumElems == NumElems) { in insert1BitVector()
6817 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in insert1BitVector()
6830 SDValue ShiftBits = DAG.getTargetConstant(NumElems - IdxVal, dl, MVT::i8); in insert1BitVector()
6846 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal; in insert1BitVector()
6850 APInt Mask0 = APInt::getBitsSet(NumElems, IdxVal, IdxVal + SubVecNumElems); in insert1BitVector()
6872 unsigned LowShift = NumElems - IdxVal; in insert1BitVector()
6879 unsigned HighShift = IdxVal + SubVecNumElems; in insert1BitVector()
19641 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); in LowerEXTRACT_VECTOR_ELT_SSE4() local
19643 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in LowerEXTRACT_VECTOR_ELT_SSE4()
19698 unsigned IdxVal = IdxC->getZExtValue(); in ExtractBitFromMaskVector() local
19699 if (IdxVal == 0) // the operation is legal in ExtractBitFromMaskVector()
19714 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in ExtractBitFromMaskVector()
19766 unsigned IdxVal = IdxC->getZExtValue(); in LowerEXTRACT_VECTOR_ELT() local
19772 Vec = extract128BitVector(Vec, IdxVal, DAG, dl); in LowerEXTRACT_VECTOR_ELT()
19780 IdxVal &= ElemsPerChunk - 1; in LowerEXTRACT_VECTOR_ELT()
19782 DAG.getIntPtrConstant(IdxVal, dl)); in LowerEXTRACT_VECTOR_ELT()
19792 if (IdxVal == 0 && !X86::mayFoldIntoZeroExtend(Op) && in LowerEXTRACT_VECTOR_ELT()
19803 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in LowerEXTRACT_VECTOR_ELT()
19816 int DWordIdx = IdxVal / 4; in LowerEXTRACT_VECTOR_ELT()
19821 int ShiftVal = (IdxVal % 4) * 8; in LowerEXTRACT_VECTOR_ELT()
19828 int WordIdx = IdxVal / 2; in LowerEXTRACT_VECTOR_ELT()
19832 int ShiftVal = (IdxVal % 2) * 8; in LowerEXTRACT_VECTOR_ELT()
19840 if (IdxVal == 0) in LowerEXTRACT_VECTOR_ELT()
19845 Mask[0] = static_cast<int>(IdxVal); in LowerEXTRACT_VECTOR_ELT()
19855 if (IdxVal == 0) in LowerEXTRACT_VECTOR_ELT()
19943 uint64_t IdxVal = N2C->getZExtValue(); in LowerINSERT_VECTOR_ELT() local
19957 CstVectorElts[IdxVal] = OnesCst; in LowerINSERT_VECTOR_ELT()
19967 BlendMask.push_back(i == IdxVal ? i + NumElts : i); in LowerINSERT_VECTOR_ELT()
19979 if (VT.is256BitVector() && IdxVal == 0) { in LowerINSERT_VECTOR_ELT()
19998 if (IdxVal >= NumEltsIn128 && in LowerINSERT_VECTOR_ELT()
20005 BlendMask.push_back(i == IdxVal ? i + NumElts : i); in LowerINSERT_VECTOR_ELT()
20010 SDValue V = extract128BitVector(N0, IdxVal, DAG, dl); in LowerINSERT_VECTOR_ELT()
20014 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1); in LowerINSERT_VECTOR_ELT()
20020 return insert128BitVector(N0, V, IdxVal, DAG, dl); in LowerINSERT_VECTOR_ELT()
20025 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(N0.getNode())) { in LowerINSERT_VECTOR_ELT()
20058 N2 = DAG.getTargetConstant(IdxVal, dl, MVT::i8); in LowerINSERT_VECTOR_ELT()
20074 if (IdxVal == 0 && (!MinSize || !X86::mayFoldLoad(N1, Subtarget))) { in LowerINSERT_VECTOR_ELT()
20089 DAG.getTargetConstant(IdxVal << 4, dl, MVT::i8)); in LowerINSERT_VECTOR_ELT()
20153 uint64_t IdxVal = Op.getConstantOperandVal(1); in LowerEXTRACT_SUBVECTOR() local
20155 if (IdxVal == 0) // the operation is legal in LowerEXTRACT_SUBVECTOR()
20172 DAG.getTargetConstant(IdxVal, dl, MVT::i8)); in LowerEXTRACT_SUBVECTOR()
54197 uint64_t IdxVal = N->getConstantOperandVal(2); in combineINSERT_SUBVECTOR() local
54217 DAG.getIntPtrConstant(IdxVal + Idx2Val, dl)); in combineINSERT_SUBVECTOR()
54224 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 && in combineINSERT_SUBVECTOR()
54246 (IdxVal != 0 || in combineINSERT_SUBVECTOR()
54258 Mask[i + IdxVal] = i + ExtIdxVal + VecNumElts; in combineINSERT_SUBVECTOR()
54284 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST) in combineINSERT_SUBVECTOR()
54289 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() && in combineINSERT_SUBVECTOR()
54304 if (IdxVal == (OpVT.getVectorNumElements() / 2) && SubVec.hasOneUse() && in combineINSERT_SUBVECTOR()
54394 unsigned IdxVal = N->getConstantOperandVal(1); in combineEXTRACT_SUBVECTOR() local
54438 InVec->ops().slice(IdxVal, NumSubElts)); in combineEXTRACT_SUBVECTOR()
54446 IdxVal == InVec.getConstantOperandVal(2) && in combineEXTRACT_SUBVECTOR()
54451 unsigned NewIdxVal = InVec.getConstantOperandVal(2) - IdxVal; in combineEXTRACT_SUBVECTOR()
54460 if (IdxVal != 0 && (InVec.getOpcode() == X86ISD::VBROADCAST || in combineEXTRACT_SUBVECTOR()
54466 if (IdxVal != 0 && InVec.getOpcode() == X86ISD::SUBV_BROADCAST_LOAD && in combineEXTRACT_SUBVECTOR()
54471 if ((InSizeInBits % SizeInBits) == 0 && (IdxVal % NumSubElts) == 0) { in combineEXTRACT_SUBVECTOR()
54479 unsigned SubVecIdx = IdxVal / NumSubElts; in combineEXTRACT_SUBVECTOR()
54498 if (IdxVal == 0 && VT == MVT::v2f64 && InVecVT == MVT::v4f64) { in combineEXTRACT_SUBVECTOR()
54515 if (IdxVal == 0 && in combineEXTRACT_SUBVECTOR()
54531 if (IdxVal == 0 && InOpcode == ISD::VSELECT && in combineEXTRACT_SUBVECTOR()
54541 if (IdxVal == 0 && InOpcode == ISD::TRUNCATE && Subtarget.hasVLX() && in combineEXTRACT_SUBVECTOR()
54553 extractSubVector(InVec.getOperand(0), IdxVal, DAG, DL, SizeInBits); in combineEXTRACT_SUBVECTOR()
54565 extractSubVector(InVec.getOperand(0), IdxVal, DAG, DL, SizeInBits); in combineEXTRACT_SUBVECTOR()