917     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);  in X86TargetLowering()
1068     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i8, Custom);  in X86TargetLowering()
1069     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);  in X86TargetLowering()
1070     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);  in X86TargetLowering()
1071     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);  in X86TargetLowering()
1102       setOperationAction(ISD::INSERT_VECTOR_ELT,  VT, Custom);  in X86TargetLowering()
1534       setOperationAction(ISD::INSERT_VECTOR_ELT,  VT, Custom);  in X86TargetLowering()
1640       setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);  in X86TargetLowering()
1877       setOperationAction(ISD::INSERT_VECTOR_ELT,  VT, Custom);  in X86TargetLowering()
2000       setOperationAction(ISD::INSERT_VECTOR_ELT,  VT, Custom);  in X86TargetLowering()
2105       setOperationAction(ISD::INSERT_VECTOR_ELT,      MVT::v32f16, Custom);  in X86TargetLowering()
2162       setOperationAction(ISD::INSERT_VECTOR_ELT,    MVT::v8f16,  Custom);  in X86TargetLowering()
2163       setOperationAction(ISD::INSERT_VECTOR_ELT,    MVT::v16f16, Custom);  in X86TargetLowering()
2327                        ISD::INSERT_VECTOR_ELT,  in X86TargetLowering()
8355   case ISD::INSERT_VECTOR_ELT: {  in getFauxShuffleMask()
8797   if (Opcode == ISD::INSERT_VECTOR_ELT &&  in getShuffleScalarElt()
8849     V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V, Op.getOperand(i),  in LowerBuildVectorAsInsert()
8915     V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, Elt,  in LowerBuildVectorv16i8()
9833   if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))  in buildFromShuffleMostly()
9894     NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),  in buildFromShuffleMostly()
9987     DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,  in LowerBUILD_VECTORvXi1()
11128       (isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT) ||  in LowerBUILD_VECTOR()
11167       return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ld, VarElt, InsIndex);  in LowerBUILD_VECTOR()
11398       Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,  in LowerBUILD_VECTOR()
19886     SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,  in InsertBitToMaskVector()
20016     V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,  in LowerINSERT_VECTOR_ELT()
22912     In = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v8i16,  in LowerFP_EXTEND()
22982       Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v4f32,  in LowerFP_ROUND()
23014   SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16,  in LowerFP16_TO_FP()
23045     Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v4f32,  in LowerFP_TO_FP16()
32233   case ISD::INSERT_VECTOR_ELT:  return LowerINSERT_VECTOR_ELT(Op, DAG);  in LowerOperation()
32909       SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecInVT,  in ReplaceNodeResults()
43725         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v4i32,  in combineArithReduction()
44037            Use->getOpcode() == ISD::INSERT_VECTOR_ELT ||  in combineExtractVectorElt()
47194           N->getOpcode() == ISD::INSERT_VECTOR_ELT) &&  in combineVectorInsert()
49165       DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, CastVT, PassThru, Load, VecIndex);  in reduceMaskedLoadToScalarLoad()
50635   case ISD::INSERT_VECTOR_ELT: {  in isFNEG()
50644         return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), VT, InsVector,  in isFNEG()
55127   case ISD::INSERT_VECTOR_ELT:  in PerformDAGCombine()