19183     MVT ExtractVT = MVT::getVectorVT(MVT::i1, SubvecElts);  in lower1BitShuffle()  local
19184     SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtractVT,  in lower1BitShuffle()
43041   EVT ExtractVT = Extract->getValueType(0);  in combineMinMaxReduction()  local
43042   if (ExtractVT != MVT::i16 && ExtractVT != MVT::i8)  in combineMinMaxReduction()
43054   if (SrcSVT != ExtractVT || (SrcVT.getSizeInBits() % 128) != 0)  in combineMinMaxReduction()
43067   assert(((SrcVT == MVT::v8i16 && ExtractVT == MVT::i16) ||  in combineMinMaxReduction()
43068           (SrcVT == MVT::v16i8 && ExtractVT == MVT::i8)) &&  in combineMinMaxReduction()
43074   unsigned MaskEltsBits = ExtractVT.getSizeInBits();  in combineMinMaxReduction()
43089   if (ExtractVT == MVT::i8) {  in combineMinMaxReduction()
43104   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtractVT, MinPos,  in combineMinMaxReduction()
43115   EVT ExtractVT = Extract->getValueType(0);  in combinePredicateReduction()  local
43116   unsigned BitWidth = ExtractVT.getSizeInBits();  in combinePredicateReduction()
43117   if (ExtractVT != MVT::i64 && ExtractVT != MVT::i32 && ExtractVT != MVT::i16 &&  in combinePredicateReduction()
43118       ExtractVT != MVT::i8 && ExtractVT != MVT::i1)  in combinePredicateReduction()
43124   if (!Match && ExtractVT == MVT::i1)  in combinePredicateReduction()
43141   if (ExtractVT == MVT::i1) {  in combinePredicateReduction()
43222     return DAG.getZExtOrTrunc(Result, DL, ExtractVT);  in combinePredicateReduction()
43243   SDValue Zext = DAG.getZExtOrTrunc(Setcc, DL, ExtractVT);  in combinePredicateReduction()
43244   SDValue Zero = DAG.getConstant(0, DL, ExtractVT);  in combinePredicateReduction()
43245   return DAG.getNode(ISD::SUB, DL, ExtractVT, Zero, Zext);  in combinePredicateReduction()
43253   EVT ExtractVT = Extract->getValueType(0);  in combineVPDPBUSDPattern()  local
43256   if (ExtractVT != MVT::i32)  in combineVPDPBUSDPattern()
43312       EVT::getVectorVT(*DAG.getContext(), ExtractVT,  in combineVPDPBUSDPattern()
43313                        DpVT.getSizeInBits() / ExtractVT.getSizeInBits());  in combineVPDPBUSDPattern()
43315   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtractVT, DP,  in combineVPDPBUSDPattern()
43325   EVT ExtractVT = Extract->getValueType(0);  in combineBasicSADPattern()  local
43328   if (ExtractVT != MVT::i32 && ExtractVT != MVT::i64)  in combineBasicSADPattern()
43384   unsigned ExtractSizeInBits = ExtractVT.getSizeInBits();  in combineBasicSADPattern()
43386   EVT ResVT = EVT::getVectorVT(*DAG.getContext(), ExtractVT,  in combineBasicSADPattern()
43389   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtractVT, SAD,  in combineBasicSADPattern()
43483     MVT ExtractVT = MVT::getVectorVT(SrcSVT.getSimpleVT(), 128 / SrcEltBits);  in combineExtractWithShuffle()  local
43484     return DAG.getNode(N->getOpcode(), dl, VT, DAG.getBitcast(ExtractVT, Src),  in combineExtractWithShuffle()
43558   EVT ExtractVT;  in combineExtractWithShuffle()  local
43561     ExtractVT = SrcVT;  in combineExtractWithShuffle()
43571     ExtractVT = EVT::getVectorVT(*DAG.getContext(), ExtractSVT, Mask.size());  in combineExtractWithShuffle()
43572     assert(SrcVT.getSizeInBits() == ExtractVT.getSizeInBits() &&  in combineExtractWithShuffle()
43586   if (SDValue V = GetLegalExtract(SrcOp, ExtractVT, ExtractIdx))  in combineExtractWithShuffle()