Lines Matching refs:DCI
39848 TargetLowering::DAGCombinerInfo &DCI, in combineTargetShuffle() argument
39868 DCI.CombineTo(N.getNode(), Movddup); in combineTargetShuffle()
39870 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
39952 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
39955 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
39959 DCI.CombineTo(LN, Scl, BcastLd.getValue(1)); in combineTargetShuffle()
39983 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
39985 DCI.recursivelyDeleteUnusedNodes(Src.getNode()); in combineTargetShuffle()
40000 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40002 DCI.recursivelyDeleteUnusedNodes(Src.getNode()); in combineTargetShuffle()
40029 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40031 DCI.recursivelyDeleteUnusedNodes(Src.getNode()); in combineTargetShuffle()
40046 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40048 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
40066 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40068 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
40084 DCI.CombineTo(N.getNode(), VZLoad); in combineTargetShuffle()
40086 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
40102 DCI.CombineTo(N.getNode(), VZLoad); in combineTargetShuffle()
40104 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
40154 if (!DCI.isBeforeLegalizeOps() && N0.hasOneUse()) { in combineTargetShuffle()
40775 TargetLowering::DAGCombinerInfo &DCI, in combineShuffle() argument
40806 if (SDValue Shuffle = combineTargetShuffle(Op, DAG, DCI, Subtarget)) in combineShuffle()
40820 if (TLI.SimplifyDemandedVectorElts(Op, DemandedElts, DCI)) in combineShuffle()
42418 TargetLowering::DAGCombinerInfo &DCI, in combineCastedMaskArithmetic() argument
42422 if (!DCI.isBeforeLegalizeOps()) in combineCastedMaskArithmetic()
42622 TargetLowering::DAGCombinerInfo &DCI, in combineBitcast() argument
42635 if (DCI.isBeforeLegalize()) { in combineBitcast()
42857 if (SDValue V = combineCastedMaskArithmetic(N, DAG, DCI, Subtarget)) in combineBitcast()
43396 TargetLowering::DAGCombinerInfo &DCI, in combineExtractWithShuffle() argument
43398 if (DCI.isBeforeLegalizeOps()) in combineExtractWithShuffle()
43883 TargetLowering::DAGCombinerInfo &DCI, in combineExtractVectorElt() argument
43885 if (SDValue NewOp = combineExtractWithShuffle(N, DAG, DCI, Subtarget)) in combineExtractVectorElt()
43919 APInt::getAllOnes(VT.getSizeInBits()), DCI)) in combineExtractVectorElt()
44021 DCI.CombineTo(Use, Res); in combineExtractVectorElt()
44042 SrcVT.getVectorElementType() == VT && DCI.isAfterLegalizeDAG() && in combineExtractVectorElt()
44064 TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) { in combineToExtendBoolVectorInReg() argument
44068 if (!DCI.isBeforeLegalizeOps()) in combineToExtendBoolVectorInReg()
44163 TargetLowering::DAGCombinerInfo &DCI, in combineVSelectWithAllOnesOrZeros() argument
44375 TargetLowering::DAGCombinerInfo &DCI, in combineVSelectToBLENDV() argument
44434 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in combineVSelectToBLENDV()
44435 !DCI.isBeforeLegalizeOps()); in combineVSelectToBLENDV()
44451 DCI.AddToWorklist(U); in combineVSelectToBLENDV()
44453 DCI.CommitTargetLoweringOpt(TLO); in combineVSelectToBLENDV()
44529 TargetLowering::DAGCombinerInfo &DCI, in combineSelect() argument
44558 if (CondConstantVector && DCI.isBeforeLegalizeOps() && in combineSelect()
44914 ISD::SIGN_EXTEND, DL, ExtCondVT, Cond, DAG, DCI, Subtarget)) { in combineSelect()
44924 if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, DCI, Subtarget)) in combineSelect()
44927 if (SDValue V = combineVSelectToBLENDV(N, DAG, DCI, Subtarget)) in combineSelect()
44954 (DCI.isBeforeLegalize() || (VT != MVT::v64i1 || Subtarget.is64Bit()))) { in combineSelect()
44983 if (DCI.isBeforeLegalize() && !Subtarget.hasAVX512() && in combineSelect()
45761 TargetLowering::DAGCombinerInfo &DCI, in combineCMov() argument
45885 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov()
46362 TargetLowering::DAGCombinerInfo &DCI, in combineMul() argument
46372 if (DCI.isBeforeLegalize() && VT.isVector()) in combineMul()
46384 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in combineMul()
46678 TargetLowering::DAGCombinerInfo &DCI, in combineShiftRightLogical() argument
46689 if (!DCI.isAfterLegalizeDAG()) in combineShiftRightLogical()
46875 TargetLowering::DAGCombinerInfo &DCI, in combineVectorPack() argument
47009 TargetLowering::DAGCombinerInfo &DCI, in combineVectorHADDSUB() argument
47057 TargetLowering::DAGCombinerInfo &DCI, in combineVectorShiftVar() argument
47081 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI)) in combineVectorShiftVar()
47088 TargetLowering::DAGCombinerInfo &DCI, in combineVectorShiftImm() argument
47182 DCI)) in combineVectorShiftImm()
47189 TargetLowering::DAGCombinerInfo &DCI, in combineVectorInsert() argument
47201 APInt::getAllOnes(NumBitsPerElt), DCI)) in combineVectorInsert()
47206 if (VT.isSimple() && DCI.isAfterLegalizeDAG()) { in combineVectorInsert()
47219 TargetLowering::DAGCombinerInfo &DCI, in combineCompareEqual() argument
47476 TargetLowering::DAGCombinerInfo &DCI, in convertIntLogicToFPLogic() argument
47498 if (N0.getOpcode() == ISD::BITCAST && !DCI.isBeforeLegalizeOps()) { in convertIntLogicToFPLogic()
47861 TargetLowering::DAGCombinerInfo &DCI, in combineAnd() argument
47920 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, DCI, Subtarget)) in combineAnd()
47923 if (DCI.isBeforeLegalizeOps()) in combineAnd()
47926 if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget)) in combineAnd()
48021 if (TLI.SimplifyDemandedVectorElts(N0, Demand0.second, DCI) || in combineAnd()
48022 TLI.SimplifyDemandedVectorElts(N1, Demand1.second, DCI) || in combineAnd()
48023 TLI.SimplifyDemandedBits(N0, Demand0.first, Demand0.second, DCI) || in combineAnd()
48024 TLI.SimplifyDemandedBits(N1, Demand1.first, Demand1.second, DCI)) { in combineAnd()
48026 DCI.AddToWorklist(N); in combineAnd()
48261 TargetLowering::DAGCombinerInfo &DCI, in combineOrCmpEqZeroToCtlzSrl() argument
48263 if (DCI.isBeforeLegalize() || !Subtarget.getTargetLowering()->isCtlzFast()) in combineOrCmpEqZeroToCtlzSrl()
48389 TargetLowering::DAGCombinerInfo &DCI, in combineOr() argument
48434 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, DCI, Subtarget)) in combineOr()
48437 if (DCI.isBeforeLegalizeOps()) in combineOr()
48440 if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget)) in combineOr()
48496 return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, DCI); in combineOr()
48500 DCI.AddToWorklist(N); in combineOr()
48961 TargetLowering::DAGCombinerInfo &DCI, in combineLoad() argument
48974 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() && in combineLoad()
49003 return DCI.CombineTo(N, NewVec, TF, true); in combineLoad()
49009 RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) { in combineLoad()
49018 return DCI.CombineTo(N, BoolVec, IntLoad.getValue(1), true); in combineLoad()
49040 return DCI.CombineTo(N, Extract, SDValue(User, 1)); in combineLoad()
49131 TargetLowering::DAGCombinerInfo &DCI, in reduceMaskedLoadToScalarLoad() argument
49167 return DCI.CombineTo(ML, Insert, Load.getValue(1), true); in reduceMaskedLoadToScalarLoad()
49172 TargetLowering::DAGCombinerInfo &DCI) { in combineMaskedLoadConstantMask() argument
49192 return DCI.CombineTo(ML, Blend, VecLd.getValue(1), true); in combineMaskedLoadConstantMask()
49216 return DCI.CombineTo(ML, Blend, NewML.getValue(1), true); in combineMaskedLoadConstantMask()
49220 TargetLowering::DAGCombinerInfo &DCI, in combineMaskedLoad() argument
49230 reduceMaskedLoadToScalarLoad(Mld, DAG, DCI, Subtarget)) in combineMaskedLoad()
49235 if (SDValue Blend = combineMaskedLoadConstantMask(Mld, DAG, DCI)) in combineMaskedLoad()
49246 if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) { in combineMaskedLoad()
49248 DCI.AddToWorklist(N); in combineMaskedLoad()
49299 TargetLowering::DAGCombinerInfo &DCI, in combineMaskedStore() argument
49320 if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) { in combineMaskedStore()
49322 DCI.AddToWorklist(N); in combineMaskedStore()
49347 TargetLowering::DAGCombinerInfo &DCI, in combineStore() argument
49400 if (!DCI.isBeforeLegalize() && VT == MVT::v64i1 && !Subtarget.is64Bit()) { in combineStore()
49471 St->getValue().hasOneUse() && !DCI.isBeforeLegalizeOps()) { in combineStore()
49527 if (DCI.isBeforeLegalize() || TLI.isTypeLegal(St->getMemoryVT())) in combineStore()
49625 TargetLowering::DAGCombinerInfo &DCI, in combineVEXTRACT_STORE() argument
49638 if (TLI.SimplifyDemandedVectorElts(StoredVal, DemandedElts, DCI)) { in combineVEXTRACT_STORE()
49640 DCI.AddToWorklist(N); in combineVEXTRACT_STORE()
50578 TargetLowering::DAGCombinerInfo &DCI) { in combineVTRUNC() argument
50590 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) in combineVTRUNC()
50746 TargetLowering::DAGCombinerInfo &DCI, in combineFneg() argument
50774 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFneg()
50893 TargetLowering::DAGCombinerInfo &DCI, in combineXor() argument
50916 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, DCI, Subtarget)) in combineXor()
50919 if (DCI.isBeforeLegalizeOps()) in combineXor()
50967 return combineFneg(N, DAG, DCI, Subtarget); in combineXor()
50971 TargetLowering::DAGCombinerInfo &DCI, in combineBEXTR() argument
50981 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) in combineBEXTR()
51072 TargetLowering::DAGCombinerInfo &DCI, in combineFOr() argument
51084 if (SDValue NewVal = combineFneg(N, DAG, DCI, Subtarget)) in combineFOr()
51179 TargetLowering::DAGCombinerInfo &DCI) { in combineX86INT_TO_FP() argument
51184 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI)) in combineX86INT_TO_FP()
51201 DCI.CombineTo(N, Convert); in combineX86INT_TO_FP()
51203 DCI.recursivelyDeleteUnusedNodes(LN); in combineX86INT_TO_FP()
51212 TargetLowering::DAGCombinerInfo &DCI) { in combineCVTP2I_CVTTP2I() argument
51232 DCI.CombineTo(N, Convert, Convert.getValue(1)); in combineCVTP2I_CVTTP2I()
51236 DCI.CombineTo(N, Convert); in combineCVTP2I_CVTTP2I()
51239 DCI.recursivelyDeleteUnusedNodes(LN); in combineCVTP2I_CVTTP2I()
51249 TargetLowering::DAGCombinerInfo &DCI, in combineAndnp() argument
51326 if (TLI.SimplifyDemandedVectorElts(N0, Demand0.second, DCI) || in combineAndnp()
51327 TLI.SimplifyDemandedVectorElts(N1, Demand1.second, DCI) || in combineAndnp()
51328 TLI.SimplifyDemandedBits(N0, Demand0.first, Demand0.second, DCI) || in combineAndnp()
51329 TLI.SimplifyDemandedBits(N1, Demand1.first, Demand1.second, DCI)) { in combineAndnp()
51331 DCI.AddToWorklist(N); in combineAndnp()
51340 TargetLowering::DAGCombinerInfo &DCI) { in combineBT() argument
51346 if (DAG.getTargetLoweringInfo().SimplifyDemandedBits(N1, DemandedMask, DCI)) { in combineBT()
51348 DCI.AddToWorklist(N); in combineBT()
51356 TargetLowering::DAGCombinerInfo &DCI) { in combineCVTPH2PS() argument
51363 if (TLI.SimplifyDemandedVectorElts(Src, DemandedElts, DCI)) { in combineCVTPH2PS()
51365 DCI.AddToWorklist(N); in combineCVTPH2PS()
51378 DCI.CombineTo(N, Convert, Convert.getValue(1)); in combineCVTPH2PS()
51382 DCI.CombineTo(N, Convert); in combineCVTPH2PS()
51386 DCI.recursivelyDeleteUnusedNodes(LN); in combineCVTPH2PS()
51668 TargetLowering::DAGCombinerInfo &DCI, in combineSext() argument
51675 if (!DCI.isBeforeLegalizeOps() && in combineSext()
51680 DCI.CombineTo(N, Setcc); in combineSext()
51685 DCI.CombineTo(N0.getNode(), Trunc); in combineSext()
51694 if (!DCI.isBeforeLegalizeOps()) in combineSext()
51701 DAG, DCI, Subtarget)) in combineSext()
51719 TargetLowering::DAGCombinerInfo &DCI, in combineFMA() argument
51749 auto invertIfNegative = [&DAG, &TLI, &DCI](SDValue &V) { in combineFMA()
51751 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMA()
51801 TargetLowering::DAGCombinerInfo &DCI) { in combineFMADDSUB() argument
51806 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMADDSUB()
51824 TargetLowering::DAGCombinerInfo &DCI, in combineZext() argument
51832 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ANY_EXTEND && in combineZext()
51837 DCI.CombineTo(N, Setcc); in combineZext()
51842 DCI.CombineTo(N0.getNode(), Trunc); in combineZext()
51851 if (DCI.isBeforeLegalizeOps()) in combineZext()
51856 DAG, DCI, Subtarget)) in combineZext()
51866 if (SDValue R = combineOrCmpEqZeroToCtlzSrl(N, DAG, DCI, Subtarget)) in combineZext()
52075 TargetLowering::DAGCombinerInfo &DCI, in combineSetCC() argument
52139 isNullConstant(RHS) && !DCI.isBeforeLegalize()) { in combineSetCC()
52219 TargetLowering::DAGCombinerInfo &DCI, in combineMOVMSK() argument
52296 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) in combineMOVMSK()
52303 TargetLowering::DAGCombinerInfo &DCI, in combineX86GatherScatter() argument
52344 if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) { in combineX86GatherScatter()
52346 DCI.AddToWorklist(N); in combineX86GatherScatter()
52379 TargetLowering::DAGCombinerInfo &DCI) { in combineGatherScatter() argument
52386 if (DCI.isBeforeLegalize()) { in combineGatherScatter()
52461 if (DCI.isBeforeLegalizeOps()) { in combineGatherScatter()
52478 if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) { in combineGatherScatter()
52480 DCI.AddToWorklist(N); in combineGatherScatter()
52669 TargetLowering::DAGCombinerInfo &DCI, in combineSIntToFP() argument
52727 if (DCI.isBeforeLegalize() || TruncVT != MVT::v2i32) { in combineSIntToFP()
53163 TargetLowering::DAGCombinerInfo &DCI) { in combineX86AddSub() argument
53188 DCI.CombineTo(GenericAddSub, Op); in combineX86AddSub()
53223 TargetLowering::DAGCombinerInfo &DCI) { in combineADC() argument
53250 return DCI.CombineTo(N, Res1, CarryOut); in combineADC()
53638 TargetLowering::DAGCombinerInfo &DCI, in combineAdd() argument
53734 TargetLowering::DAGCombinerInfo &DCI, in combineSub() argument
53813 TargetLowering::DAGCombinerInfo &DCI, in combineConcatVectorOps() argument
54163 TargetLowering::DAGCombinerInfo &DCI, in combineCONCAT_VECTORS() argument
54176 DCI, Subtarget)) in combineCONCAT_VECTORS()
54184 TargetLowering::DAGCombinerInfo &DCI, in combineINSERT_SUBVECTOR() argument
54186 if (DCI.isBeforeLegalizeOps()) in combineINSERT_SUBVECTOR()
54268 combineConcatVectorOps(dl, OpVT, SubVectorOps, DAG, DCI, Subtarget)) in combineINSERT_SUBVECTOR()
54377 TargetLowering::DAGCombinerInfo &DCI, in combineEXTRACT_SUBVECTOR() argument
54421 if (DCI.isBeforeLegalizeOps()) in combineEXTRACT_SUBVECTOR()
54644 TargetLowering::DAGCombinerInfo &DCI, in combinePMULDQ() argument
54661 if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(64), DCI)) in combinePMULDQ()
54697 TargetLowering::DAGCombinerInfo &DCI) { in combineVPMADD() argument
54710 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI)) in combineVPMADD()
54717 TargetLowering::DAGCombinerInfo &DCI, in combineEXTEND_VECTOR_INREG() argument
54727 if (!DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(In.getNode()) && in combineEXTEND_VECTOR_INREG()
54761 if (!DCI.isBeforeLegalizeOps() && Opcode == ISD::ZERO_EXTEND_VECTOR_INREG && in combineEXTEND_VECTOR_INREG()
54787 TargetLowering::DAGCombinerInfo &DCI) { in combineKSHIFT() argument
54795 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI)) in combineKSHIFT()
54902 TargetLowering::DAGCombinerInfo &DCI) { in combineBROADCAST_LOAD() argument
54931 return DCI.CombineTo(N, Extract, SDValue(User, 1)); in combineBROADCAST_LOAD()
55015 TargetLowering::DAGCombinerInfo &DCI) { in combinePDEP() argument
55018 if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(NumBits), DCI)) in combinePDEP()
55025 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
55026 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
55034 return combineExtractVectorElt(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55036 return combineCONCAT_VECTORS(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55038 return combineINSERT_SUBVECTOR(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55040 return combineEXTRACT_SUBVECTOR(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55043 case X86ISD::BLENDV: return combineSelect(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55044 case ISD::BITCAST: return combineBitcast(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55045 case X86ISD::CMOV: return combineCMov(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55047 case ISD::ADD: return combineAdd(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55048 case ISD::SUB: return combineSub(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55050 case X86ISD::SUB: return combineX86AddSub(N, DAG, DCI); in PerformDAGCombine()
55052 case X86ISD::ADC: return combineADC(N, DAG, DCI); in PerformDAGCombine()
55053 case ISD::MUL: return combineMul(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55056 case ISD::SRL: return combineShiftRightLogical(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55057 case ISD::AND: return combineAnd(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55058 case ISD::OR: return combineOr(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55059 case ISD::XOR: return combineXor(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55061 case X86ISD::BEXTRI: return combineBEXTR(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55062 case ISD::LOAD: return combineLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55063 case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55064 case ISD::STORE: return combineStore(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55065 case ISD::MSTORE: return combineMaskedStore(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55067 return combineVEXTRACT_STORE(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55070 return combineSIntToFP(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55078 case ISD::FNEG: return combineFneg(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55080 case X86ISD::VTRUNC: return combineVTRUNC(N, DAG, DCI); in PerformDAGCombine()
55081 case X86ISD::ANDNP: return combineAndnp(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55085 case X86ISD::FOR: return combineFOr(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55091 case X86ISD::CVTUI2P: return combineX86INT_TO_FP(N, DAG, DCI); in PerformDAGCombine()
55098 return combineCVTP2I_CVTTP2I(N, DAG, DCI); in PerformDAGCombine()
55100 case X86ISD::CVTPH2PS: return combineCVTPH2PS(N, DAG, DCI); in PerformDAGCombine()
55101 case X86ISD::BT: return combineBT(N, DAG, DCI); in PerformDAGCombine()
55103 case ISD::ZERO_EXTEND: return combineZext(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55104 case ISD::SIGN_EXTEND: return combineSext(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55109 return combineEXTEND_VECTOR_INREG(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55110 case ISD::SETCC: return combineSetCC(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55114 case X86ISD::PACKUS: return combineVectorPack(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55118 case X86ISD::FHSUB: return combineVectorHADDSUB(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55122 return combineVectorShiftVar(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55126 return combineVectorShiftImm(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55129 case X86ISD::PINSRW: return combineVectorInsert(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55164 case ISD::VECTOR_SHUFFLE: return combineShuffle(N, DAG, DCI,Subtarget); in PerformDAGCombine()
55176 case ISD::STRICT_FMA: return combineFMA(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55180 case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, DCI); in PerformDAGCombine()
55181 case X86ISD::MOVMSK: return combineMOVMSK(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55184 return combineX86GatherScatter(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55186 case ISD::MSCATTER: return combineGatherScatter(N, DAG, DCI); in PerformDAGCombine()
55190 case X86ISD::PMULUDQ: return combinePMULDQ(N, DAG, DCI, Subtarget); in PerformDAGCombine()
55192 case X86ISD::VPMADDWD: return combineVPMADD(N, DAG, DCI); in PerformDAGCombine()
55194 case X86ISD::KSHIFTR: return combineKSHIFT(N, DAG, DCI); in PerformDAGCombine()
55201 case X86ISD::SUBV_BROADCAST_LOAD: return combineBROADCAST_LOAD(N, DAG, DCI); in PerformDAGCombine()
55203 case X86ISD::PDEP: return combinePDEP(N, DAG, DCI); in PerformDAGCombine()