24344         unsigned CC0, CC1;  in LowerVSETCC()  local
24347           CC0 = 3; // UNORD  in LowerVSETCC()
24352           CC0 = 7; // ORD  in LowerVSETCC()
24361               {Chain, Op0, Op1, DAG.getTargetConstant(CC0, dl, MVT::i8)});  in LowerVSETCC()
24369               Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(CC0, dl, MVT::i8));  in LowerVSETCC()
45288 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,  in checkBoolTestAndOrSetCCCombine()  argument
45320   CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);  in checkBoolTestAndOrSetCCCombine()
45928     X86::CondCode CC0, CC1;  in combineCMov()  local
45930     if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {  in combineCMov()
45933         CC0 = X86::GetOppositeBranchCondition(CC0);  in combineCMov()
45938                         DAG.getTargetConstant(CC0, DL, MVT::i8), Flags};  in combineCMov()
47508   ISD::CondCode CC0 = cast<CondCodeSDNode>(N0.getOperand(2))->get();  in convertIntLogicToFPLogic()  local
47514       !(cheapX86FSETCC_SSE(CC0) && cheapX86FSETCC_SSE(CC1)))  in convertIntLogicToFPLogic()
47531   SDValue Setcc0 = DAG.getSetCC(DL, BoolVecVT, Vec00, Vec01, CC0);  in convertIntLogicToFPLogic()