Lines Matching refs:BitIdx

7665       int BitIdx = N->getConstantOperandVal(2);  in getTargetShuffleMask()  local
7666 DecodeEXTRQIMask(NumElems, MaskEltSize, BitLen, BitIdx, Mask); in getTargetShuffleMask()
7676 int BitIdx = N->getConstantOperandVal(3); in getTargetShuffleMask() local
7677 DecodeINSERTQIMask(NumElems, MaskEltSize, BitLen, BitIdx, Mask); in getTargetShuffleMask()
11909 int BitIdx = ExpectedIdx < Size ? ExpectedIdx : (ExpectedIdx - Size); in isTargetShuffleEquivalent() local
11911 ZeroMask.setBit(BitIdx); in isTargetShuffleEquivalent()
13739 uint64_t &BitIdx, const APInt &Zeroable) { in matchShuffleAsEXTRQ() argument
13785 BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f; in matchShuffleAsEXTRQ()
13795 uint64_t &BitIdx) { in matchShuffleAsINSERTQ() argument
13848 BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f; in matchShuffleAsINSERTQ()
13862 uint64_t BitLen, BitIdx; in lowerShuffleWithSSE4A() local
13863 if (matchShuffleAsEXTRQ(VT, V1, V2, Mask, BitLen, BitIdx, Zeroable)) in lowerShuffleWithSSE4A()
13866 DAG.getTargetConstant(BitIdx, DL, MVT::i8)); in lowerShuffleWithSSE4A()
13868 if (matchShuffleAsINSERTQ(VT, V1, V2, Mask, BitLen, BitIdx)) in lowerShuffleWithSSE4A()
13872 DAG.getTargetConstant(BitIdx, DL, MVT::i8)); in lowerShuffleWithSSE4A()
38278 uint64_t BitLen, BitIdx; in combineX86ShuffleChain() local
38279 if (matchShuffleAsEXTRQ(IntMaskVT, V1, V2, Mask, BitLen, BitIdx, in combineX86ShuffleChain()
38286 DAG.getTargetConstant(BitIdx, DL, MVT::i8)); in combineX86ShuffleChain()
38290 if (matchShuffleAsINSERTQ(IntMaskVT, V1, V2, Mask, BitLen, BitIdx)) { in combineX86ShuffleChain()
38297 DAG.getTargetConstant(BitIdx, DL, MVT::i8)); in combineX86ShuffleChain()
44138 int BitIdx = (i % EltSizeInBits); in combineToExtendBoolVectorInReg() local
44139 APInt Bit = APInt::getBitsSet(EltSizeInBits, BitIdx, BitIdx + 1); in combineToExtendBoolVectorInReg()