411   Register DestReg = I->getOperand(0).getReg();  in searchALUInst()  local
423         if (Opnd.getReg() == DestReg) {  in searchALUInst()
444         if (TRI->regsOverlap(DestReg, Opnd.getReg()))  in searchALUInst()
572   Register DestReg = MI.getOperand(0).getReg();  in optTwoAddrLEA()  local
577   if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))  in optTwoAddrLEA()
594       (DestReg == BaseReg || DestReg == IndexReg)) {  in optTwoAddrLEA()
596     if (DestReg != BaseReg)  in optTwoAddrLEA()
601       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
606       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
609   } else if (DestReg == BaseReg && IndexReg == 0) {  in optTwoAddrLEA()
623         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
626         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
633         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
637         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
765   Register DestReg = Dest.getReg();  in processInstrForSlow3OpLEA()  local
782   if (IsInefficientBase && DestReg == BaseReg && !IsScale1)  in processInstrForSlow3OpLEA()
794   if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) {  in processInstrForSlow3OpLEA()
796     if (DestReg != BaseReg)  in processInstrForSlow3OpLEA()
801       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
807       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
835         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
836                     .addReg(DestReg);  in processInstrForSlow3OpLEA()
840         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
841                     .addReg(DestReg)  in processInstrForSlow3OpLEA()
854   assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");  in processInstrForSlow3OpLEA()
864     TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);  in processInstrForSlow3OpLEA()
868     NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
869                 .addReg(DestReg)  in processInstrForSlow3OpLEA()
891   NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
892               .addReg(DestReg)  in processInstrForSlow3OpLEA()