Lines Matching refs:vec
169 foreach vec = AllVecs in {
170 defm : LoadPatNoOffset<vec.vt, load, "LOAD_V128">;
171 defm : LoadPatImmOff<vec.vt, load, regPlusImm, "LOAD_V128">;
172 defm : LoadPatImmOff<vec.vt, load, or_is_add, "LOAD_V128">;
173 defm : LoadPatOffsetOnly<vec.vt, load, "LOAD_V128">;
174 defm : LoadPatGlobalAddrOffOnly<vec.vt, load, "LOAD_V128">;
207 foreach vec = AllVecs in {
208 defvar inst = "LOAD"#vec.lane_bits#"_SPLAT";
209 defm : LoadPatNoOffset<vec.vt, load_splat, inst>;
210 defm : LoadPatImmOff<vec.vt, load_splat, regPlusImm, inst>;
211 defm : LoadPatImmOff<vec.vt, load_splat, or_is_add, inst>;
212 defm : LoadPatOffsetOnly<vec.vt, load_splat, inst>;
213 defm : LoadPatGlobalAddrOffOnly<vec.vt, load_splat, inst>;
217 multiclass SIMDLoadExtend<Vec vec, string loadPat, bits<32> simdop> {
218 defvar signed = vec.prefix#".load"#loadPat#"_s";
219 defvar unsigned = vec.prefix#".load"#loadPat#"_u";
221 defm LOAD_EXTEND_S_#vec#_A32 :
227 defm LOAD_EXTEND_U_#vec#_A32 :
233 defm LOAD_EXTEND_S_#vec#_A64 :
239 defm LOAD_EXTEND_U_#vec#_A64 :
252 foreach vec = [I16x8, I32x4, I64x2] in
256 defvar loadpat = !cast<PatFrag>(exts[0]#vec.split.lane_bits);
257 defvar inst = "LOAD_EXTEND"#exts[1]#"_"#vec;
258 defm : LoadPatNoOffset<vec.vt, loadpat, inst>;
259 defm : LoadPatImmOff<vec.vt, loadpat, regPlusImm, inst>;
260 defm : LoadPatImmOff<vec.vt, loadpat, or_is_add, inst>;
261 defm : LoadPatOffsetOnly<vec.vt, loadpat, inst>;
262 defm : LoadPatGlobalAddrOffOnly<vec.vt, loadpat, inst>;
266 multiclass SIMDLoadZero<Vec vec, bits<32> simdop> {
267 defvar name = "v128.load"#vec.lane_bits#"_zero";
269 defm LOAD_ZERO_#vec#_A32 :
275 defm LOAD_ZERO_#vec#_A64 :
298 foreach vec = [I32x4, I64x2] in {
299 defvar inst = "LOAD_ZERO_"#vec;
301 (vector_insert (vec.splat (vec.lane_vt 0)), (vec.lane_vt (load $ptr)), 0)>;
302 defm : LoadPatNoOffset<vec.vt, pat, inst>;
303 defm : LoadPatImmOff<vec.vt, pat, regPlusImm, inst>;
304 defm : LoadPatImmOff<vec.vt, pat, or_is_add, inst>;
305 defm : LoadPatOffsetOnly<vec.vt, pat, inst>;
306 defm : LoadPatGlobalAddrOffOnly<vec.vt, pat, inst>;
310 multiclass SIMDLoadLane<Vec vec, bits<32> simdop> {
311 defvar name = "v128.load"#vec.lane_bits#"_lane";
313 defm LOAD_LANE_#vec#_A32 :
316 I32:$addr, V128:$vec),
318 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
320 defm LOAD_LANE_#vec#_A64 :
323 I64:$addr, V128:$vec),
325 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
336 multiclass LoadLanePatNoOffset<Vec vec, SDPatternOperator kind> {
337 defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32");
338 defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64");
339 def : Pat<(vec.vt (kind (i32 I32:$addr),
340 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
341 (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>,
343 def : Pat<(vec.vt (kind (i64 I64:$addr),
344 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
345 (load_lane_a64 0, 0, imm:$idx, $addr, $vec)>,
350 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
351 (vector_insert $vec, (i32 (extloadi8 $ptr)), $idx)>;
353 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
354 (vector_insert $vec, (i32 (extloadi16 $ptr)), $idx)>;
356 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
357 (vector_insert $vec, (i32 (load $ptr)), $idx)>;
359 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
360 (vector_insert $vec, (i64 (load $ptr)), $idx)>;
374 SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
376 "v128.store\t${off}(${addr})$p2align, $vec",
379 SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr, V128:$vec),
381 "v128.store\t${off}(${addr})$p2align, $vec",
386 foreach vec = AllVecs in {
387 defm : StorePatNoOffset<vec.vt, store, "STORE_V128">;
388 defm : StorePatImmOff<vec.vt, store, regPlusImm, "STORE_V128">;
389 defm : StorePatImmOff<vec.vt, store, or_is_add, "STORE_V128">;
390 defm : StorePatOffsetOnly<vec.vt, store, "STORE_V128">;
391 defm : StorePatGlobalAddrOffOnly<vec.vt, store, "STORE_V128">;
395 multiclass SIMDStoreLane<Vec vec, bits<32> simdop> {
396 defvar name = "v128.store"#vec.lane_bits#"_lane";
398 defm STORE_LANE_#vec#_A32 :
401 I32:$addr, V128:$vec),
403 [], name#"\t${off}(${addr})$p2align, $vec, $idx",
405 defm STORE_LANE_#vec#_A64 :
408 I64:$addr, V128:$vec),
410 [], name#"\t${off}(${addr})$p2align, $vec, $idx",
421 multiclass StoreLanePatNoOffset<Vec vec, SDPatternOperator kind> {
422 def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
423 (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, 0, imm:$idx, $addr, $vec)>,
425 def : Pat<(kind (i64 I64:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
426 (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, 0, imm:$idx, $addr, $vec)>,
431 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
432 (truncstorei8 (i32 (vector_extract $vec, $idx)), $ptr)>;
434 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
435 (truncstorei16 (i32 (vector_extract $vec, $idx)), $ptr)>;
437 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
438 (store (i32 (vector_extract $vec, $idx)), $ptr)>;
440 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
441 (store (i64 (vector_extract $vec, $idx)), $ptr)>;
456 multiclass ConstVec<Vec vec, dag ops, dag pat, string args> {
458 defm CONST_V128_#vec : SIMD_I<(outs V128:$dst), ops, (outs), ops,
459 [(set V128:$dst, (vec.vt pat))],
544 foreach vec = AllVecs in {
545 def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y),
573 multiclass Splat<Vec vec, bits<32> simdop> {
574 defm SPLAT_#vec : SIMD_I<(outs V128:$dst), (ins vec.lane_rc:$x),
576 [(set (vec.vt V128:$dst),
577 (vec.splat vec.lane_rc:$x))],
578 vec.prefix#".splat\t$dst, $x", vec.prefix#".splat",
590 foreach vec = AllVecs in
591 def : Pat<(vec.vt (scalar_to_vector (vec.lane_vt vec.lane_rc:$x))),
592 (!cast<Instruction>("SPLAT_"#vec) $x)>;
599 multiclass ExtractLane<Vec vec, bits<32> simdop, string suffix = ""> {
600 defm EXTRACT_LANE_#vec#suffix :
601 SIMD_I<(outs vec.lane_rc:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
603 vec.prefix#".extract_lane"#suffix#"\t$dst, $vec, $idx",
604 vec.prefix#".extract_lane"#suffix#"\t$idx", simdop>;
616 def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)),
617 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
618 def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)),
619 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
620 def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)),
621 (EXTRACT_LANE_I32x4 $vec, imm:$idx)>;
622 def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)),
623 (EXTRACT_LANE_F32x4 $vec, imm:$idx)>;
624 def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)),
625 (EXTRACT_LANE_I64x2 $vec, imm:$idx)>;
626 def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)),
627 (EXTRACT_LANE_F64x2 $vec, imm:$idx)>;
630 (sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8),
631 (EXTRACT_LANE_I8x16_s $vec, imm:$idx)>;
633 (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)),
634 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
636 (sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16),
637 (EXTRACT_LANE_I16x8_s $vec, imm:$idx)>;
639 (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)),
640 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
643 multiclass ReplaceLane<Vec vec, bits<32> simdop> {
644 defm REPLACE_LANE_#vec :
645 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, vec.lane_rc:$x),
648 (vec.vt V128:$vec),
649 (vec.lane_vt vec.lane_rc:$x),
650 (i32 vec.lane_idx:$idx)))],
651 vec.prefix#".replace_lane\t$dst, $vec, $idx, $x",
652 vec.prefix#".replace_lane\t$idx", simdop>;
663 def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
664 (REPLACE_LANE_I8x16 $vec, 0, $x)>;
665 def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
666 (REPLACE_LANE_I16x8 $vec, 0, $x)>;
667 def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
668 (REPLACE_LANE_I32x4 $vec, 0, $x)>;
669 def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
670 (REPLACE_LANE_I64x2 $vec, 0, $x)>;
671 def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
672 (REPLACE_LANE_F32x4 $vec, 0, $x)>;
673 def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
674 (REPLACE_LANE_F64x2 $vec, 0, $x)>;
680 multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop> {
681 defm _#vec :
683 [(set (vec.int_vt V128:$dst),
684 (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))],
685 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
686 vec.prefix#"."#name, simdop>;
755 multiclass SIMDBinary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> {
756 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
758 [(set (vec.vt V128:$dst),
759 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
760 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
761 vec.prefix#"."#name, simdop>;
770 foreach vec = IntVecs in
771 def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
775 multiclass SIMDUnary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> {
776 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins),
777 [(set (vec.vt V128:$dst),
778 (vec.vt (node (vec.vt V128:$v))))],
779 vec.prefix#"."#name#"\t$dst, $v",
780 vec.prefix#"."#name, simdop>;
786 foreach vec = IntVecs in
787 def : Pat<(vnot (vec.vt V128:$v)), (NOT $v)>;
803 foreach vec = AllVecs in
804 def : Pat<(vec.vt (int_wasm_bitselect
805 (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))),
809 foreach vec = IntVecs in
810 def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)),
811 (and (vnot V128:$c), (vec.vt V128:$v2)))),
815 foreach vec = AllVecs in
816 def : Pat<(vec.vt (vselect
817 (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))),
825 foreach vec = AllVecs in {
826 def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
833 (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
838 (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
840 } // foreach vec
866 defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [],
867 "v128.any_true\t$dst, $vec", "v128.any_true", 0x53>;
869 foreach vec = IntVecs in
870 def : Pat<(int_wasm_anytrue (vec.vt V128:$vec)), (ANYTRUE V128:$vec)>;
873 multiclass SIMDAllTrue<Vec vec, bits<32> simdop> {
874 defm ALLTRUE_#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
876 (i32 (int_wasm_alltrue (vec.vt V128:$vec))))],
877 vec.prefix#".all_true\t$dst, $vec",
878 vec.prefix#".all_true", simdop>;
899 defvar vec = !cast<Vec>(reduction[2]);
900 def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
901 def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>;
902 def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
905 multiclass SIMDBitmask<Vec vec, bits<32> simdop> {
906 defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
908 (i32 (int_wasm_bitmask (vec.vt V128:$vec))))],
909 vec.prefix#".bitmask\t$dst, $vec", vec.prefix#".bitmask",
922 multiclass SIMDShift<Vec vec, SDNode node, string name, bits<32> simdop> {
923 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), (outs), (ins),
924 [(set (vec.vt V128:$dst), (node V128:$vec, I32:$x))],
925 vec.prefix#"."#name#"\t$dst, $vec, $x",
926 vec.prefix#"."#name, simdop>;
1040 foreach vec = [I8x16, I16x8] in {
1041 defvar inst = !cast<NI>("AVGR_U_"#vec);
1044 (add_nuw (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
1045 (vec.splat (i32 1))),
1064 multiclass SIMDExtBinary<Vec vec, SDPatternOperator node, string name,
1066 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
1068 [(set (vec.vt V128:$dst), (node
1069 (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))],
1070 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
1071 vec.prefix#"."#name, simdop>;
1180 foreach vec = [F32x4, F64x2] in {
1181 defvar pmin = !cast<NI>("PMIN_"#vec);
1182 defvar pmax = !cast<NI>("PMAX_"#vec);
1183 def : Pat<(vec.int_vt (vselect
1184 (setolt (vec.vt (bitconvert V128:$rhs)),
1185 (vec.vt (bitconvert V128:$lhs))),
1188 def : Pat<(vec.int_vt (vselect
1189 (setolt (vec.vt (bitconvert V128:$lhs)),
1190 (vec.vt (bitconvert V128:$rhs))),
1209 multiclass SIMDConvert<Vec vec, Vec arg, SDPatternOperator op, string name,
1211 defm op#_#vec :
1212 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
1213 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
1214 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
1248 multiclass SIMDExtend<Vec vec, bits<32> baseInst> {
1249 defm "" : SIMDConvert<vec, vec.split, extend_low_s,
1250 "extend_low_"#vec.split.prefix#"_s", baseInst>;
1251 defm "" : SIMDConvert<vec, vec.split, extend_high_s,
1252 "extend_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>;
1253 defm "" : SIMDConvert<vec, vec.split, extend_low_u,
1254 "extend_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>;
1255 defm "" : SIMDConvert<vec, vec.split, extend_high_u,
1256 "extend_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>;
1264 multiclass SIMDNarrow<Vec vec, bits<32> baseInst> {
1265 defvar name = vec.split.prefix#".narrow_"#vec.prefix;
1266 defm NARROW_S_#vec.split :
1268 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed
1269 (vec.vt V128:$low), (vec.vt V128:$high))))],
1271 defm NARROW_U_#vec.split :
1273 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_unsigned
1274 (vec.vt V128:$low), (vec.vt V128:$high))))],
1350 multiclass RelaxedConvert<Vec vec, Vec arg, SDPatternOperator op, string name, bits<32> simdop> {
1351 defm op#_#vec :
1352 RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
1353 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
1354 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
1370 multiclass SIMDFM<Vec vec, bits<32> simdopA, bits<32> simdopS> {
1371 defm FMA_#vec :
1373 [(set (vec.vt V128:$dst), (int_wasm_fma
1374 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1375 vec.prefix#".relaxed_fma\t$dst, $a, $b, $c",
1376 vec.prefix#".relaxed_fma", simdopA>;
1377 defm FMS_#vec :
1379 [(set (vec.vt V128:$dst), (int_wasm_fms
1380 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1381 vec.prefix#".relaxed_fms\t$dst, $a, $b, $c",
1382 vec.prefix#".relaxed_fms", simdopS>;
1392 multiclass SIMDLANESELECT<Vec vec, bits<32> op> {
1393 defm LANESELECT_#vec :
1395 [(set (vec.vt V128:$dst), (int_wasm_laneselect
1396 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1397 vec.prefix#".relaxed_laneselect\t$dst, $a, $b, $c",
1398 vec.prefix#".relaxed_laneselect", op>;
1410 multiclass RelaxedBinary<Vec vec, SDPatternOperator node, string name,
1412 defm _#vec : RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
1414 [(set (vec.vt V128:$dst),
1415 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
1416 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
1417 vec.prefix#"."#name, simdop>;