Lines Matching refs:DestReg

328                             MCRegister DestReg, MCRegister SrcReg, bool KillSrc,  in copyPhysSubRegs()  argument
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); in copyPhysSubRegs()
354 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysSubRegs()
361 MCRegister DestReg, MCRegister SrcReg, in copyPhysReg() argument
364 if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { in copyPhysReg()
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
368 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) in copyPhysReg()
387 } else if (VE::VMRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
391 } else if (VE::VM512RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
395 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ANDMmm), in copyPhysReg()
397 } else if (VE::F128RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
401 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri), in copyPhysReg()
406 << " to " << printReg(DestReg, TRI) << "\n"; in copyPhysReg()
523 Register DestReg, int FI, in loadRegFromStackSlot() argument
537 BuildMI(MBB, I, DL, get(VE::LDrii), DestReg) in loadRegFromStackSlot()
543 BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg) in loadRegFromStackSlot()
549 BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg) in loadRegFromStackSlot()
555 BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg) in loadRegFromStackSlot()
561 BuildMI(MBB, I, DL, get(VE::LDVMrii), DestReg) in loadRegFromStackSlot()
567 BuildMI(MBB, I, DL, get(VE::LDVM512rii), DestReg) in loadRegFromStackSlot()